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HIGH-SPEED 3.3V 64K x 36

ASYNCHRONOUS DUAL-PORT

STATIC RAM

Features

True Dual-Port memory cells which allow simultaneous

access of the same memory location

High-speed access

鈥?Commercial: 10/12/15ns (max.)

鈥?Industrial: 12/15ns (max.)

Dual chip enables allow for depth expansion without

external logic

IDT70V658 easily expands data bus width to 72 bits or

more using the Master/Slave select when cascading more

than one device

M/S = V

IH

for

BUSY

output flag on Master,

M/S = V

IL

for

BUSY

input on Slave

Busy and Interrupt Flags

On-chip port arbitration logic

x

x

x

PRELIMINARY

IDT70V658S

x

x

x

x

x

x

x

x

x

x

x

x

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

Separate byte controls for multiplexed bus and bus

matching compatibility

Supports JTAG features compliant to IEEE 1149.1

LVTTL-compatible, single 3.3V (鹵150mV) power supply

for core

LVTTL-compatible, selectable 3.3V (鹵150mV)/2.5V (鹵100mV)

power supply for I/Os and control signals on each port

Available in 208-pin Plastic Quad Flatpack, 208-ball fine

pitch Ball Grid Array, and 256-ball Ball Grid Array

Industrial temperature range (鈥?0擄C to +85擄C) is available

for selected speeds

Functional Block Diagram

BE

3L

BE

2L

BE

3 R

BE

2 R

BE

1R

BE

0R

R/

W

R

B

E

0

L

B

E

1

L

B

E

2

L

B

E

3

L

B

E

3

R

BB

EE

2 1

RR

B

E

0

R

BE

1 L

BE

0L

R/

W

L

CE

0 L

CE1 L

CE

0 R

CE1R

OE

L

OE

R

Dout0-8_L

Dout9-17_L

Dout18-26_L

Dout27-35_L

Dout0-8_R

Dout9-17_R

Dout18-26_R

Dout27-35_R

64K x 36

MEMORY

ARRAY

I/O - I/O

0L

35L

Di n_L

Di n_R

I/O - I/O

0R

35R

A15 L

A0 L

Address

Decoder

ADDR_L

ADDR_R

Address

Decoder

A

15R

A

0R

CE

0 L

CE1L

OE

L

R/WL

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

CE

0 R

CE1R

OE

R

R/WR

BUSY

R

BUSY

L

SEM

L

INT

L

M/S

SEM

R

INT

R

TDI

TDO

JTAG

TMS

TCK

TRST

5613 drw 01

NOTES:

1.

BUSY

is an input as a Slave (M/S=V

IL

) and an output when it is a Master (M/S=V

IH

).

2.

BUSY

and

INT

are non-tri-state totem-pole outputs (push-pull).

JUNE 2001

DSC-5613/3

1

漏2001 Integrated Device Technology, Inc.

next

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