HIGH-SPEED 3.3V 128K x 18
ASYNCHRONOUS DUAL-PORT
STATIC RAM
x
PRELIMINARY
IDT70V639S
Features
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed access
鈥?Commercial: 10/12/15ns (max.)
鈥?Industrial: 12/15ns (max.)
Dual chip enables allow for depth expansion without
external logic
IDT70V639 easily expands data bus width to 36 bits or
more using the Master/Slave select when cascading more
than one device
M/S = V
IH
for
BUSY
output flag on Master,
M/S = V
IL
for
BUSY
input on Slave
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
UB
L
LB
L
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Fully asynchronous operation from either port
Separate byte controls for multiplexed bus and bus
matching compatibility
Supports JTAG features compliant to IEEE 1149.1
鈥?Due to limited pin count, JTAG is not supported on the
128-pin TQFP package.
LVTTL-compatible, single 3.3V (鹵150mV) power supply for
core
LVTTL-compatible, selectable 3.3V (鹵150mV)/2.5V (鹵100mV)
power supply for I/Os and control signals on each port
Available in a 128-pin Thin Quad Flatpack, 208-ball fine
pitch Ball Grid Array, and 256-ball Ball Grid Array
Industrial temperature range (鈥?0擄C to +85擄C) is available
for selected speeds
Functional Block Diagram
UB
R
LB
R
R/W
L
B
E
0
L
B
E
1
L
B
E
1
R
B
E
0
R
R/W
R
CE
0L
CE
1L
CE
0R
CE
1R
OE
L
Dout0-8_L
Dout9-17_L
Dout0-8_R
Dout9-17_R
OE
R
128K x 18
MEMORY
ARRAY
I/O
0L
- I/O
17L
Din_L
Din_R
I/O
0R
- I/O
17R
A
16L
A
0L
Address
Decoder
ADDR_L
ADDR_R
Address
Decoder
A
16R
A
0R
OE
L
CE
0L
CE
1L
R/W
L
BUSY
L
SEM
L
INT
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
OE
R
CE
0R
CE
1R
R/W
R
BUSY
R
M/S
SEM
R
INT
R
TDI
TDO
JTAG
TMS
TCK
TRST
5621 drw 01
NOTES:
1.
BUSY
is an input as a Slave (M/S=V
IL
) and an output when it is a Master (M/S=V
IH
).
2.
BUSY
and
INT
are non-tri-state totem-pole outputs (push-pull).
JUNE 2001
DSC-5621/3
1
漏2001 Integrated Device Technology, Inc.