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IDT70V3399S133PRFI Datasheet

  • IDT70V3399S133PRFI

  • HIGH-SPEED 3.3V 256/128K x 18 SYNCHRONOUS DUAL-PORT STATIC R...

  • 23頁

  • IDT

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HIGH-SPEED 3.3V
256/128K x 18
IDT70V3319/99S
SYNCHRONOUS
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
Features:
鈼?/div>
鈼?/div>
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鈼?/div>
鈼?/div>
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True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed data access
鈥?Commercial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
鈥?Industrial: 4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode
鈥?Due to limited pin count PL/
FT
option is not supported
on the 128-pin TQFP package. Device is pipelined
outputs only on each port.
Counter enable and repeat features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
鈥?6ns cycle time, 166MHz operation (6Gbps bandwidth)
鈥?Fast 3.6ns clock to data out
鈥?1.7ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 166MHz
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鈥?Data input, address, byte enable and control registers
鈥?Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus
matching compatibility
Dual Cycle Deselect (DCD) for Pipelined Output mode
LVTTL- compatible, single 3.3V (鹵150mV) power supply
for core
LVTTL compatible, selectable 3.3V (鹵150mV) or 2.5V
(鹵100mV) power supply for I/Os and control signals on
each port
Industrial temperature range (-40擄C to +85擄C) is
available at 133MHz.
Available in a 128-pin Thin Quad Flatpack, 208-pin fine
pitch Ball Grid Array, and 256-pin Ball
Grid Array
Supports JTAG features compliant to IEEE 1149.1
鈥?Due to limited pin count, JTAG is not supported on the
128-pin TQFP package.
Functional Block Diagram
UB
L
LB
L
UB
R
LB
R
FT/PIPE
L
1/0
0a 1a
a
0b 1b
b
1b 0b
b
1a 0a
a
1/0
FT/PIPE
R
R/W
L
CE
0L
CE
1L
1
0
1/0
B
W
0
L
B
W
1
L
B B
WW
1 0
R R
1
0
1/0
R/W
R
CE
0R
CE
1R
OE
L
Dout0-8_L
Dout9-17_L
Dout0-8_R
Dout9-17_R
OE
R
1b 0b 1a 0a
0a 1a 0b 1b
0/1
,
FT/PIPE
R
FT/PIPE
L
0/1
ab
ba
256K x 18
MEMORY
ARRAY
I/O
0L
- I/O
17L
Din_L
Din_R
I/O
0R
- I/O
17R
CLK
L
A
17L(1)
A
0L
REPEAT
L
ADS
L
CNTEN
L
CLK
R
,
A
17R(1)
Counter/
Address
Reg.
ADDR_L
ADDR_R
Counter/
Address
Reg.
A
0R
REPEAT
R
ADS
R
CNTEN
R
5623 tbl 01
TDI
NOTE:
1. A
17
is a NC for IDT70V3399.
JTAG
TDO
TCK
TMS
TRST
MAY 2003
1
DSC 5623/7
漏2003 Integrated Device Technology, Inc.

IDT70V3399S133PRFI 產品屬性

  • 6

  • 集成電路 (IC)

  • 存儲器

  • -

  • RAM

  • SRAM - 雙端口，同步

  • 2M（128K x 18）

  • 133MHz

  • 并聯

  • 3.15 V ~ 3.45 V

  • -40°C ~ 85°C

  • 128-LQFP

  • 128-TQFP（14x20）

  • 托盤

  • 70V3399S133PRFI

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