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HIGH-SPEED 3.3V

16K x 16 DUAL-PORT

STATIC RAM

Features

True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

High-speed access

鈥?Commercial: 25/35/55ns (max.)

Low-power operation

鈥?IDT70V26S

Active: 300mW (typ.)

Standby: 3.3mW (typ.)

鈥?IDT70V26L

Active: 300mW (typ.)

Standby: 660

碌

W (typ.)

Separate upper-byte and lower-byte control for multiplexed

bus compatibility

x

IDT70V26S/L

x

x

x

x

x

x

x

x

x

x

x

IDT70V26 easily expands data bus width to 32 bits or more

using the Master/Slave select when cascading more than

one device

M/S = V

IH

for

BUSY

output flag on Master

M/S = V

IL

for

BUSY

input on Slave

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

TTL-compatible, single 3.3V (鹵0.3V) power supply

Available in 84-pin PGA and PLCC

Industrial temperature range (-40擄C to +85擄C) is available

for selected speeds

Functional Block Diagram

R/W

L

UB

L

R/W

R

UB

R

LB

L

CE

L

OE

L

LB

R

CE

R

OE

R

I/O

8L

-I/O

15L

I/O

Control

I/O

0L

-I/O

7L

BUSY

L

A

13L

A

0L

(1,2)

I/O

8R

-I/O

15R

I/O

Control

I/O

0R

-I/O

7R

BUSY

R

Address

Decoder

14

(1,2)

MEMORY

ARRAY

14

Address

Decoder

A

13R

A

0R

CE

L

ARBITRATION

SEMAPHORE

LOGIC

CE

R

SEM

L

M/S

NOTES:

1. (MASTER):

BUSY

is output; (SLAVE):

BUSY

is input.

2.

BUSY

outputs are non-tri-stated push-pull.

SEM

R

2945 drw 01

JUNE 2000

1

漏2000 Integrated Device Technology, Inc.

DSC 2945/13

next

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