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IDT70V09L20PFI Datasheet

  • IDT70V09L20PFI

  • HIGH-SPEED 3.3V 128K x 8 DUAL-PORT STATIC RAM

  • 17頁

  • IDT

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HIGH-SPEED 3.3V
128K x 8 DUAL-PORT
STATIC RAM
Features
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IDT70V09L
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True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed access
鈥?Commercial: 15/20ns (max.)
鈥?Industrial: 20ns (max.)
Low-power operation
鈥?IDT70V09L
Active: 440mW (typ.)
Standby: 660碌W (typ.)
Dual chip enables allow for depth expansion without
external logic
IDT70V09 easily expands data bus width to 16 bits or
more using the Master/Slave select when cascading more
than one device
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M/S = V
IH
for
BUSY
output flag on Master,
M/S = V
IL
for
BUSY
input on Slave
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
LVTTL-compatible, single 3.3V (鹵0.3V) power supply
Available in a 100-pin TQFP
Industrial temperature range (鈥?0擄C to +85擄C) is available
for selected speeds
Functional Block Diagram
R/W
L
CE
0L
CE
1L
OE
L
R/W
R
CE
0R
CE
1R
OE
R
I/O
0-7L
I/O
Control
(1,2)
I/O
Control
I/O
0-7R
(1,2)
BUSY
L
A
16L
A
0L
BUSY
R
128Kx8
MEMORY
ARRAY
70V09
17
17
Address
Decoder
Address
Decoder
A
16R
A
0R
CE
0L
CE
1L
OE
L
R/W
L
SEM
L
(2)
INT
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
0R
CE
1R
OE
R
R/W
R
SEM
R
(2)
INT
R
4852 drw 01
(1)
M/S
NOTES:
1.
BUSY
is an input as a Slave (M/S=V
IL
) and an output when it is a Master (M/S=V
IH
).
2.
BUSY
and
INT
are non-tri-state totem-pole outputs (push-pull).
SEPTEMBER 2003
DSC-4852/4
1
漏2003 Integrated Device Technology, Inc.

IDT70V09L20PFI 產品屬性

  • 12

  • 集成電路 (IC)

  • 存儲器

  • -

  • RAM

  • SRAM - 雙端口，異步

  • 1M (128K x 8)

  • 20ns

  • 并聯

  • 3 V ~ 3.6 V

  • -40°C ~ 85°C

  • 100-LQFP

  • 100-TQFP（14x14）

  • 托盤

  • 70V09L20PFI800-2605IDT70V09L20PFI-ND

IDT70V09L20PFI相關型號PDF文件下載

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