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IDT70T653MS10BC Datasheet

  • IDT70T653MS10BC

  • HIGH-SPEED 2.5V 512K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM ...

  • 308.70KB

  • 24頁(yè)

  • IDT

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Features
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HIGH-SPEED 2.5V
512K x 36
ASYNCHRONOUS DUAL-PORT
STATIC RAM
WITH 3.3V 0R 2.5V INTERFACE
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PRELIMINARY
IDT70T653M
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True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed access
鈥?Commercial: 10/12/15ns (max.)
鈥?Industrial: 12ns (max.)
RapidWrite Mode simplifies high-speed consecutive write
cycles
Dual chip enables allow for depth expansion without
external logic
IDT70T653M easily expands data bus width to 72 bits or
more using the Busy Input when cascading more than one
device
Busy input for port contention management
Interrupt Flags
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Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Separate byte controls for multiplexed bus and bus
matching compatibility
Sleep Mode Inputs on both ports
Single 2.5V (鹵100mV) power supply for core
LVTTL-compatible, selectable 3.3V (鹵150mV)/2.5V (鹵100mV)
power supply for I/Os and control signals on each port
Includes JTAG functionality
Available in a 256-ball Ball Grid Array
Industrial temperature range (鈥?0擄C to +85擄C) is available
for selected speeds
Functional Block Diagram
BE
3L
BE
2L
BE
1L
BE
0L
BE
3R
BE
2R
BE
1R
BE
0R
R/
W
L
CE
0L
CE
1L
BB
EE
01
LL
BB
EE
23
LL
BBBB
EEEE
3210
R RRR
R/
W
R
CE
0R
CE
1R
OE
L
Dout0-8_L
Dout0-8_R
Dout9-17_L
Dout9-17_R
Dout18-26_L Dout18-26_R
Dout27-35_L Dout27-35_R
OE
R
512K x 36
MEMORY
ARRAY
I/O
0L-
I/O
35L
Di n_L
Di n_R
I/O
0R -
I/O
35R
A
18L
A
0L
Address
Decoder
ADDR_L
ADDR_R
Address
Decoder
A
18R
A
0R
CE
0L
CE
1L
OE
L
R/W
L
BUSY
L
SEM
L
INT
L(1)
ZZ
L(2)
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
OE
R
R/W
R
CE
0R
CE
1R
TDI
TD O
JTAG
TC K
TMS
TRST
BUSY
R
SEM
R
INT
R(1)
ZZ
CONTROL
LOGIC
ZZ
R(2)
NOTES:
1.
INT
is non-tri-state totem-pole outputs (push-pull).
2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx,
INTx
and the sleep mode
pins themselves (ZZx) are not affected during sleep mode.
5679 drw 01
NOVEMBER 2003
DSC-5679/2
1
漏2003 Integrated Device Technology, Inc.

IDT70T653MS10BC 產(chǎn)品屬性

  • 6

  • 集成電路 (IC)

  • 存儲(chǔ)器

  • -

  • RAM

  • SRAM - 雙端口，異步

  • 18M（512K x 36）

  • 10ns

  • 并聯(lián)

  • 2.4 V ~ 2.6 V

  • 0°C ~ 70°C

  • 256-LBGA

  • 256-CABGA（17x17）

  • 托盤

  • 70T653MS10BC

IDT70T653MS10BC相關(guān)型號(hào)PDF文件下載

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