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IDT70T3539MS133BC Datasheet

  • IDT70T3539MS133BC

  • HIGH-SPEED 2.5V 512K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM W...

  • 26頁

  • IDT

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Features:
鈼?/div>
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HIGH-SPEED 2.5V
512K x 36
SYNCHRONOUS
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
PRELIMINARY
IDT70T3539M
鈼?/div>
鈼?/div>
鈼?/div>
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True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed data access
鈥?Commercial: 3.6ns (166MHz)/4.2ns (133MHz)(max.)
鈥?Industrial: 4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode
Counter enable and repeat features
Dual chip enables allow for depth expansion without
additional logic
Interrupt and Collision Detection Flags
Full synchronous operation on both ports
鈥?6ns cycle time, 166MHz operation (12Gbps bandwidth)
鈥?Fast 3.6ns clock to data out
鈥?1.5ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 166MHz
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鈥?Data input, address, byte enable and control registers
鈥?Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus
matching compatibility
Dual Cycle Deselect (DCD) for Pipelined Output Mode
2.5V (鹵100mV) power supply for core
LVTTL compatible, selectable 3.3V (鹵150mV) or 2.5V
(鹵100mV) power supply for I/Os and control signals on
each port
Includes JTAG functionality
Industrial temperature range (-40擄C to +85擄C) is
available at 133MHz
Available in a 256-pin Ball Grid Array (BGA)
Functional Block Diagram
BE
3L
BE
2L
BE
1L
BE
0L
BE
3R
BE
2R
BE
1R
BE
0R
FT/PIPE
L
1/0
0a 1a
a
0b 1b
b
0c 1c
c
0d 1d
d
1d 0d
d
1c 0c
c
1b 0b
b
1a 0a
a
1/0
FT/PIPE
R
R/W
L
R/W
R
CE
0L
CE
1L
1
0
1/0
B B B B B
W W WWW
0 1 2 3 3
L L L L R
B B B
W WW
2 1 0
R R R
1
0
1/0
CE
0R
CE
1R
OE
L
OE
R
Dout0-8_L
Dout9-17_L
Dout18-26_L
Dout27-35_L
Dout0-8_R
Dout9-17_R
Dout18-26_R
Dout27-35_R
1d 0d 1c 0c 1b 0b 1a 0a
0a 1a 0b 1b 0c 1c 0d 1d
0/1
,
FT/PIPE
R
FT/PIPE
L
0/1
a bc d
d cba
512K x 36
MEMORY
ARRAY
I/O
0L
- I/O
35L
Din_L
Din_R
I/O
0R
- I/O
35R
CLK
L
A
18L
A
0L
REPEAT
L
ADS
L
CNTEN
L
A
18R
CLK
R
,
Counter/
Address
Reg.
ADDR_L
ADDR_R
Counter/
Address
Reg.
A
0R
REPEAT
R
ADS
R
CNTEN
R
TDI
TCK
TMS
TRST
CE
0 L
CE1 L
R/
W
L
INTERRUPT
COLLISION
DE TE CTION
LOGIC
CE
0 R
CE1 R
R /
W
R
JTAG
TDO
COL
R
INT
R
COL
L
INT
L
ZZ
L
(1)
ZZ
CONTROL
LOGIC
ZZ
R
(1)
5678 drw 01
NOTE:
1. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and OPTx and
the sleep mode pins themselves (ZZx) are not affected during sleep mode.
APRIL 2004
DSC 5678/5
1
漏2004 Integrated Device Technology, Inc.

IDT70T3539MS133BC 產(chǎn)品屬性

  • 6

  • 集成電路 (IC)

  • 存儲器

  • -

  • RAM

  • SRAM - 雙端口，同步

  • 18M（512K x 36）

  • 133MHz

  • 并聯(lián)

  • 2.4 V ~ 2.6 V

  • 0°C ~ 70°C

  • 256-LBGA

  • 256-CABGA（17x17）

  • 托盤

  • 70T3539MS133BC800-1381

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