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IDT70T3319S200DDI Datasheet

  • IDT70T3319S200DDI

  • HIGH-SPEED 2.5V 512/256/128K X 18 SYNCHRONOUS DUAL-PORT STAT...

  • 28頁

  • IDT

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HIGH-SPEED 2.5V
PRELIMINARY
512/256/128K X 18
IDT70T3339/19/99S
SYNCHRONOUS
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
Features:
鈼?/div>
鈼?/div>
鈼?/div>
鈼?/div>
鈼?/div>
鈼?/div>
鈼?/div>
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed data access
鈥?Commercial: 3.4 (200MHz)/3.6ns (166MHz)/
4.2ns (133MHz)(max.)
鈥?Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode
Counter enable and repeat features
Dual chip enables allow for depth expansion without
additional logic
Interrupt and Collision Detection Flags
Full synchronous operation on both ports
鈥?5ns cycle time, 200MHz operation (14Gbps bandwidth)
鈥?Fast 3.4ns clock to data out
鈥?1.5ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 200MHz
鈼?/div>
鈼?/div>
鈼?/div>
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鈼?/div>
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鈼?/div>
鈥?Data input, address, byte enable and control registers
鈥?Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus
matching compatibility
Dual Cycle Deselect (DCD) for Pipelined Output Mode
2.5V (鹵100mV) power supply for core
LVTTL compatible, selectable 3.3V (鹵150mV) or 2.5V
(鹵100mV) power supply for I/Os and control signals on
each port
Industrial temperature range (-40擄C to +85擄C) is
available at 166MHz and 133MHz
Available in a 256-pin Ball Grid Array (BGA), a 144-pin Thin
Quad Flatpack (TQFP) and 208-pin fine pitch Ball Grid Array
(fpBGA)
Supports JTAG features compliant with IEEE 1149.1
Due to limited pin count JTAG, Collision Detection and
Interrupt are not supported on the 144-pin TQFP package
Functional Block Diagram
UB
L
LB
L
UB
R
LB
R
FT/PIPE
L
1/0
0a 1a
a
0b 1b
b
1b 0b
b
1a 0a
a
1/0
FT
/PIPE
R
R/W
L
CE
0L
CE
1L
1
0
1/0
B B
WW
0 1
L L
B B
WW
1 0
R R
1
0
1/0
R/
W
R
CE
0R
CE
1R
OE
L
Dout0-8_L
Dout9-17_L
Dout0-8_R
Dout9-17_R
OE
R
1b 0b 1a 0a
FT/PIPE
L
0/1
0a 1a 0b
1b
,
0/1
FT
/PIPE
R
ab
512/256/128K x 18
MEMORY
ARRAY
ba
I/O
0L
- I/O
17L
Din_L
Din_R
I/O
0R
- I/O
17R
CLK
L
A
18L(1)
A
0L
REPEAT
L
ADS
L
CNTEN
L
A
18R(1)
CLK
R
,
Counter/
Address
Reg.
ADDR_L
ADDR_R
Counter/
Address
Reg.
A
0R
REPEAT
R
ADS
R
CNTEN
R
TDI
TCK
TMS
TRST
CE
0 L
CE1L
R/
W
L
INTERRUPT
COLLISION
DETECTION
LOGIC
CE
0 R
CE1 R
R/
W
R
JTAG
TDO
COL
L
INT
L
COL
R
INT
R
ZZ
L
(2)
ZZ
CONTROL
LOGIC
ZZ
R
(2)
5652 drw 01
NOTES:
1. Address A
18
is a NC for the IDT70T3319. Also, Addresses A
18
and A
17
are NC's for the IDT70T3399.
2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and
OPTx and the sleep mode pins themselves (ZZx) are not affected during sleep mode.
NOVEMBER 2003
DSC-5652/3
1
漏2003 Integrated Device Technology, Inc.

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