鈼?/div>
select when cascading more than one device
M/S = V
IH
for
BUSY
output flag on Master
M/S = V
IL
for
BUSY
input on Slave
BUSY
and Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
LVTTL-compatible, single 1.8V (鹵100mV) power supply
Available in a 100-pin Thin Quad Flatpack (TQFP) package,
100-pin 0.8mm pitch Ball Grid Array (fpBGA), and 100-pin
0.5mm pitch BGA (fpBGA)
Industrial temperature range (-40擄C to +85擄C) is available
for selected speeds
Functional Block Diagram
R/W
L
UB
L
R/W
R
UB
R
LB
CE
L
L
OE
L
LB
R
CE
R
OE
R
,
I/O
9L
-I/O
17L
(5)
I/O
0L
-I/O
8L
(4)
BUSY
L
A
12L
(1)
A
0L
(2,3)
I/O
9R
-I/O
17R
(5)
I/O
Control
I/O
Control
I/O
0R
-I/O
8R
(4)
BUSY
R
(2,3)
Address
Decoder
13
MEMORY
ARRAY
13
Address
Decoder
A
12R
(1)
A
0R
CE
L
OE
L
R/W
L
SEM
L
(3)
INT
L
NOTES:
1. A
12
is a NC for IDT70P34 and IDT70P24.
2. (MASTER):
BUSY
is output; (SLAVE):
BUSY
is input.
3.
BUSY
outputs and
INT
outputs are non-tri-stated push-pull.
4. I/O
0
x - I/O
7
x for IDT70P25/24.
5. I/O
8
x - I/O
15
x for IDT70P25/24.
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/W
R
SEM
R
INT
R
(3)
5683 drw 01
M/S
FEBRUARY 2004
1
DSC-5683/2
漏2004 Integrated Device Technology, Inc.