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IDT70P248 Datasheet

  • IDT70P248

  • VERY LOW POWER 1.8V 8K/4K x 16 DUAL-PORT STATIC RAM

  • 23頁

  • IDT

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VERY LOW POWER 1.8V
8K/4K x 16 DUAL-PORT
STATIC RAM
Features
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IDT70P258/248L
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True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
鈥?Industrial: 55ns (max.)
Low-power operation
IDT70P258/248L
Active: 27mW (typ.)
Standby: 3.6
碌
W (typ.)
Separate upper-byte and lower-byte control for multiplexed
bus compatibility
IDT70P258/248 easily expands data bus width to 32 bits or
more using the Master/Slave select when cascading more
than one device
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Supports 3.0V, 2.5V and 1.8V I/O's
M/S = V
DD
for
BUSY
output flag on Master
M/S = V
SS
for
BUSY
input on Slave
Input Read Register
Output Drive Register
BUSY
and Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
LVTTL-compatible, single 1.8V (鹵100mV) power supply
Available in 100 Ball 0.5mm-pitch BGA
Industrial temperature range (-40擄C to +85擄C)
Functional Block Diagram
R/W
L
UB
L
R/W
R
UB
R
LB
L
CE
L
OE
L
LB
R
CE
R
OE
R
I/O
8L
-I/O
15L
I/O
0L
-I/O
7L
BUSY
L
(2,3)
I/O
8R
-I/O
15R
I/O
Control
I/O
Control
I/O
0R
-I/O
7R
BUSY
R
(2,3)
,
A
12L
(1)
A
0L
Address
Decoder
MEMORY
ARRAY
Address
Decoder
A
12R
(1)
A
0R
CE
L
OE
L
R/W
L
IRR
0
,IRR
1
INPUT
READ REGISTER
AND
OUTPUT
DRIVE REGISTER
SFEN
13
13
CE
R
OE
R
R/W
R
ODR
0
-
ODR
4
CE
L
OE
L
R/W
L
SEM
L
(3)
INT
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/W
R
SEM
R
INT
R
(3)
5675 drw 01
M/S
NOTES:
1. A
12X
is a NC for IDT70P248.
2. (MASTER):
BUSY
is output; (SLAVE):
BUSY
is input.
3.
BUSY
outputs and
INT
outputs are non-tri-stated push-pull.
APRIL 2004
1
DSC-5675/4
漏2004 Integrated Device Technology, Inc.

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