HIGH-SPEED 64K x 8
SYNCHRONOUS
DUAL-PORT STATIC RAM
Features:
x
x
PRELIMINARY
IDT709089S/L
x
x
x
x
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
鈥?Commercial: 9/12/15ns (max.)
Low-power operation
鈥?IDT709089S
Active: 950mW (typ.)
Standby: 5mW (typ.)
鈥?IDT709089L
Active: 950mW (typ.)
Standby: 1mW (typ.)
Flow-Through or Pipelined output mode on either port via
the
FT/PIPE
pin
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
x
x
x
x
Full synchronous operation on both ports
鈥?4ns setup to clock and 1ns hold on all control, data,
and address inputs
鈥?Data input, address, and control registers
鈥?Fast 9ns clock to data out in the Pipelined output mode
鈥?Self-timed write allows fast cycle time
鈥?15ns cycle time, 66MHz operation in the Pipelined
output mode
TTL- compatible, single 5V (鹵10%) power supply
Industrial temperature range (鈥?0擄C to +85擄C) is available
for selected speeds
Available in 100-pin Thin Quad Flatpack (TQFP) package
Functional Block Diagram
R/
W
L
OE
L
R/
W
R
OE
R
1
0
0/1
1
0
0/1
CE
0L
CE
1L
CE
0R
CE
1R
FT
/PIPE
L
0/1
1
0
0
1
0/1
FT
/PIPE
R
I/O
0L
- I/O
7L
I/O
Control
I/O
Control
I/O
0R
- I/O
7R
A
15L
A
0L
CLK
L
Counter/
Address
Reg.
MEMORY
ARRAY
Counter/
Address
Reg.
A
15R
A
0R
CLK
R
ADS
L
CNTEN
L
CNTRST
L
ADS
R
CNTEN
R
CNTRST
R
3242 drw 01
FEBRUARY 2000
1
漏2000 Integrated Device Technology, Inc.
DSC-3242/10