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IDT70824L45GB Datasheet

  • IDT70824L45GB

  • HIGH-SPEED 4K X 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY (S...

  • 205.91KB

  • 21頁(yè)

  • IDT

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HIGH SPEED 64K (4K X 16 BIT)
IDT70824S/L
SEQUENTIAL ACCESS
RANDOM ACCESS MEMORY (SARAM
鈩?/div>
)
Features
x
x
x
x
x
x
x
x
High-speed access
鈥?Military: 35/45ns (max.)
鈥?Commercial: 20/25/35/45ns (max.)
Low-power operation
鈥?IDT70824S
Active: 775mW (typ.)
Standby: 5mW (typ.)
鈥?IDT70824L
Active: 775mW (typ.)
Standby: 1mW (typ.)
4K x 16 Sequential Access Random Access Memory (SARAM
鈩?/div>
)
鈥?Sequential Access from one port and standard Random
Access from the other port
鈥?Separate upper-byte and lower-byte control of the
Random Access Port
High speed operation
鈥?20ns t
AA
for random access port
鈥?20ns t
CD
for sequential port
鈥?25ns clock cycle time
Architecture based on Dual-Port RAM cells
x
x
x
x
x
Compatible with Intel BMIC and 82430 PCI Set
Width and Depth Expandable
Sequential side
鈥?Address based flags for buffer control
鈥?Pointer logic supports up to two internal buffers
Battery backup operation - 2V data retention
TTL-compatible, single 5V (+10%) power supply
Available in 80-pin TQFP and 84-pin PGA
Military product compliant to MIL-PRF-38535 QML
Industrial temperature range (鈥?0擄C to +85擄C) is available
for selected speeds
Description
The IDT70824 is a high-speed 4K x 16-Bit Sequential Access Random
Access Memory (SARAM). The SARAM offers a single-chip solution to
buffer data sequentially on one port, and be accessed randomly (asyn-
chronously) through the other port. The device has a Dual-Port RAM
based architecture with a standard SRAM interface for the random
(asynchronous) access port, and a clocked interface with counter se-
Functional Block Diagram
A
0-11
CE
OE
R/W
LB
LSB
MSB
UB
CMD
I/O
0-15
12
Random
Access
Port
Controls
Sequential
Access
Port
Controls
4K X 16
Memory
Array
16
12
12
12
12
12
RST
SCLK
CNTEN
SOE
SSTRT
1
SSTRT
2
SCE
SR/W
SLD
SI/O
0-15
,
Data
L
Addr
L
Data
R
Addr
R
16
Reg.
12
16
RST
Pointer/
Counter
Start Address for Buffer #1
End Address for Buffer #1
Start Address for Buffer #2
End Address for Buffer #2
Flow Control Buffer
Flag Status
12
EOB
1
COMPARATOR
EOB
2
3099 drw 01
APRIL 2000
1
漏2000 Integrated Device Technology, Inc.
DSC-3099/5
6.07

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