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HIGH-SPEED

4K x 18 DUAL-PORT

STATIC RAM

Features:

x

x

IDT7034S/L

x

x

x

True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

High-speed access

聴 Commercial: 15/20ns (max.)

Low-power operation

聴 IDT7034S

Active: 850mW (typ.)

Standby: 5mW (typ.)

聴 IDT7034L

Active: 850mW (typ.)

Standby: 1mW (typ.)

Separate upper-byte and lower-byte control for multiplexed

bus compatibility

IDT7034 easily expands data bus width to 36 bits or more

x

x

x

x

x

x

x

x

x

using the Master/Slave select when cascading more than

one device

M/S = H for

BUSY

output flag on Master

M/S = L for

BUSY

input on Slave

Interrupt Flag

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

Battery backup operation聴2V data retention

TTL-compatible, single 5V (鹵10%) power supply

Available in 100-pin Thin Quad Flatpack

Industrial temperature range (聳40擄C to +85擄C) is available

for selected speeds

Functional Block Diagram

R/

W

L

UB

L

R/

W

R

UB

R

LB

L

CE

L

OE

L

LB

R

CE

R

OE

R

I/O

9L

-I/O

17L

I/O

0L

-I/O

8L

BUSY

L

(1,2)

I/O

Control

I/O

Control

I/O

9R

-I/O

17R

I/O

0R

-I/O

8R

BUSY

R

(1,2)

.

A

11L

A

0L

Address

Decoder

13

MEMORY

ARRAY

13

Address

Decoder

A

11R

A

0R

CE

L

OE

L

R/

W

L

SEM

L

(2)

INT

L

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

CE

R

OE

R

R/

W

R

SEM

R

(2)

INT

R

4089 drw 01

M/

S

NOTES:

1. (MASTER):

BUSY

is output; (SLAVE):

BUSY

is input.

2.

BUSY

outputs and

INT

outputs are non-tri-stated push-pull.

SEPTEMBER 1999

1

漏1999 Integrated Device Technology, Inc.

DSC 4089/6

next

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