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HIGH-SPEED

32K x 16 DUAL-PORT

STATIC RAM

Features

x

x

IDT7027S/L

x

x

x

True Dual-Ported memory cells which allow simultaneous

access of the same memory location

High-speed access

鈥?Military: 25/35/55ns (max)

鈥?Industrial: 25ns (max.)

鈥?Commercial: 20/25/35/55ns (max.)

Low-power operation

鈥?IDT7027S

Active: 750mW (typ.)

Standby: 5mW (typ.)

鈥?IDT7027L

Active: 750mW (typ.)

Standby: 1mW (typ.)

Separate upper-byte and lower-byte control for bus

matching capability.

Dual chip enables allow for depth expansion without

x

x

x

x

x

x

x

x

x

external logic

IDT7027 easily expands data bus width to 32 bits or more

using the Master/Slave select when cascading more than

one device

M/S = V

IH

for

BUSY

output flag on Master,

M/S = V

IL

for

BUSY

input on Slave

Busy and Interrupt Flags

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

TTL-compatible, single 5V (鹵10%) power supply

Available in 100-pin Thin Quad Flatpack (TQFP) and 108-pin

Ceramic Pin Grid Array (PGA)

Industrial temperature range (鈥?0擄C to +85擄C) is available

for selected speeds

Functional Block Diagram

R/

W

L

UB

L

CE

0L

CE

1L

OE

L

LB

L

R/

W

R

UB

R

CE

0R

CE

1R

OE

R

LB

R

I/O

8-15L

I/O

0-7L

BUSY

L

(1,2)

A

14L

A

0L

32Kx16

MEMORY

ARRAY

7027

I/O

Control

I/O

Control

I/O

8-15R

I/O

0-7R

BUSY

R

A

14R

A

0R

(1,2)

.

Address

Decoder

A

14L

A

0L

CE

0L

CE

1L

OE

L

R/W

L

Address

Decoder

A

14R

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

A

0R

CE

0R

CE

1R

OE

R

R/W

R

SEM

R

(2)

INT

R

3199 drw 01

SEM

L

INT

L

(2)

M/S

(2)

NOTES:

1.

BUSY

is an input as a Slave (M/S=V

IL

) and an output as a Master (M/S=V

IH

).

2.

BUSY

and

INT

are non-tri-state totem-pole outputs (push-pull).

MAY 2000

DSC 3199/7

1

漏2000 Integrated Device Technology, Inc.

next

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