鈥?/div>
more than one device
M/
S
= H for
BUSY
output flag on Master
M/
S
= L for
BUSY
input on Slave
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Devices are capable of withstanding greater than 2001V
electrostatic discharge.
Fully asynchronous operation from either port
Battery backup operation鈥?V data retention
TTL-compatible, single 5V (鹵10%) power supply
Available in 84-pin PGA, 84-pin quad flatpack, 84-pin
PLCC, and 100-pin Thin Quad Plastic Flatpack
Industrial temperature range (鈥?0擄C to +85擄C) is avail-
able, tested to military electrical specifications
FUNCTIONAL BLOCK DIAGRAM
R/
W
L
UB
L
R/
W
R
UB
R
LB
L
CE
L
OE
L
LB
R
CE
R
OE
R
I/O
8L
-I/O
15L
I/O
Control
I/O
0L
-I/O
7L
I/O
Control
I/O
8R
-I/O
15R
I/O
0R
-I/O
7R
BUSY
L
(1,2)
BUSY
R(1,2)
Address
Decoder
12
A
11L
A
0L
MEMORY
ARRAY
12
Address
Decoder
A
11R
A
0R
NOTES:
1. (MASTER):
BUSY
is output;
(SLAVE):
BUSY
is input.
2.
BUSY
outputs
and
INT
outputs
are non-tri-stated
push-pull.
CE
L
OE
L
R/
W
L
SEM
L
(2)
INT
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/
W
R
SEM
R
INT
R(2)
2740 drw 01
M/
S
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
漏1996 Integrated Device Technology, Inc.
For latest information contact IDT鈥檚 web site at www.idt.com or fax-on-demand at 408-492-8391.
OCTOBER 1996
DSC-2740/6
6.15
1