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IDT70125L55J Datasheet

  • IDT70125L55J

  • HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT

  • 12頁(yè)

  • IDT

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HIGH-SPEED
2K x 9 DUAL-PORT
STATIC RAM WITH BUSY & INTERRUPT
Integrated Device Technology, Inc.
IDT70121S/L
IDT70125S/L
FEATURES:
鈥?High-speed access
鈥?Commercial: 25/35/45/55ns (max.)
鈥?Low-power operation
鈥?IDT70121/70125S
Active: 500mW (typ.)
Standby: 5mW (typ.)
鈥?IDT70121/70125L
Active: 500mW (typ.)
Standby: 1mW (typ.)
鈥?Fully asychronous operation from either port
鈥?MASTER IDT70121 easily expands data bus width to 18
bits or more using SLAVE IDT70125 chip
鈥?On-chip port arbitration logic (IDT70121 only)
鈥?/div>
BUSY
output flag on Master;
BUSY
input on Slave
鈥?/div>
INT
flag for port-to-port communication
鈥?Battery backup operation鈥?V data retention
鈥?TTL-compatible, signal 5V (鹵10%) power supply
鈥?Available in 52-pin PLCC
鈥?Industrial temperature range (鈥?0擄C to +85擄C) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT70121/IDT70125 are high-speed 2K x 9 Dual-Port
Static RAMs. The IDT70121 is designed to be used as a
stand-alone 9-bit Dual-Port RAM or as a 鈥淢ASTER鈥?Dual-Port
RAM together with the IDT70125 鈥淪LAVE鈥?Dual-Port in 18-
bit-or-more word width systems. Using the IDT MASTER/
SLAVE Dual-Port RAM approach in 18-bit-or-wider memory
system applications results in full-speed, error-free operation
without the need for additional discrete logic.
Both devices provide two independent ports with separate
control, address, and I/O pins that permit independent, asyn-
chronous access for reads or writes to any location in memory.
An automatic power-down feature, controlled by
CE
, permits
the on-chip circuitry of each port to enter a very low standby
power mode.
The IDT70121/IDT70125 utilizes a 9-bit wide data path to
allow for Data/Control and parity bits at the user鈥檚 option. This
feature is especially useful in data communications
applications where it is necessary to use a parity bit for
transmission/reception error checking.
FUNCTIONAL BLOCK DIAGRAM
OE
L
CE
L
R/
W
L
OE
R
R/
W
R
CE
R
I/O
0L
- I/O
8L
I/O
Control
I/O
Control
I/O
0R
-I/O
8R
BUSY
L
(1,2)
BUSY
R
Address
Decoder
11
(1,2)
A
10L
A
0L
MEMORY
ARRAY
Address
Decoder
A
11R
A
0R
11
NOTES:
1. 70121 (MASTER):
BUSY
is non-tri-
stated push-pull
output.
70125 (SLAVE):
BUSY
is input.
2.
INT
is totem-pole
output.
CE
L
OE
L
R/
W
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/
W
R
INT
L(2)
INT
R
2654 drw 01
(2)
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
漏1996 Integrated Device Technology, Inc.
For latest information contact IDT鈥檚 web site at www.idt.com or fax-on-demand at 408-492-8391.
OCTOBER 1996
DSC-2654/4
6.10
1

IDT70125L55J 產(chǎn)品屬性

  • 24

  • 集成電路 (IC)

  • 存儲(chǔ)器

  • -

  • RAM

  • SRAM - 雙端口，異步

  • 18K（2K x 9）

  • 55ns

  • 并聯(lián)

  • 4.5 V ~ 5.5 V

  • 0°C ~ 70°C

  • 52-LCC（J 形引線）

  • 52-PLCC（19x19）

  • 管件

  • 70125L55J

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