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HIGH-SPEED

64K x 8 DUAL-PORT

STATIC RAM

Features

x

x

x

IDT7008S/L

x

x

True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

High-speed access

鈥?Military: 25/35/55ns (max.)

鈥?Industrial: 55ns (max.)

鈥?Commercial: 20/25/35/55ns (max.)

Low-power operation

鈥?IDT7008S

Active: 750mW (typ.)

Standby: 5mW (typ.)

鈥?IDT7008L

Active: 750mW (typ.)

Standby: 1mW (typ.)

Dual chip enables allow for depth expansion without

external logic

x

x

x

x

x

x

x

x

IDT7008 easily expands data bus width to 16 bits or

more using the Master/Slave select when cascading more

than one device

M/S = V

IH

for

BUSY

output flag on Master,

M/S = V

IL

for

BUSY

input on Slave

Interrupt Flag

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

TTL-compatible, single 5V (鹵10%) power supply

Available in 84-pin PGA, 84-pin PLCC, and a 100-pin TQFP

Industrial temperature range (鈥?0擄C to +85擄C) is available

for selected speeds

Functional Block Diagram

R/W

L

CE

0L

CE

1L

OE

L

R/W

R

CE

0R

CE

1R

OE

R

I/O

0-7L

I/O

Control

I/O

Control

I/O

0-7R

BUSY

L

A

15L

A

0L

(1,2)

BUSY

R

64Kx8

MEMORY

ARRAY

7008

16

16

(1,2)

Address

Decoder

Address

Decoder

A

15R

A

0R

CE

0L

CE

1L

OE

L

R/W

L

SEM

L

(2)

INT

L

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

CE

0R

CE

1R

OE

R

R/W

R

SEM

R

(2)

INT

R

3198 drw 01

M/S

(1)

NOTES:

1.

BUSY

is an input as a Slave (M/S = V

IL

) and an output when it is a Master (M/S = V

IH

).

2.

BUSY

and

INT

are non-tri-state totem-pole outputs (push-pull).

MAY 2000

DSC 3198/6

1

漏2000 Integrated Device Technology, Inc.

next

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