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HIGH-SPEED

32K x 8 DUAL-PORT

STATIC RAM

Features

x

x

IDT7007S/L

x

x

True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

High-speed access

聳 Military: 25/35/55ns (max.)

聳 Industrial: 55ns (max.)

聳 Commercial: 15/20/25/35/55ns (max.)

Low-power operation

聳 IDT7007S

Active: 850mW (typ.)

Standby: 5mW (typ.)

聳 IDT7007L

Active: 850mW (typ.)

Standby: 1mW (typ.)

IDT7007 easily expands data bus width to 16 bits or more

x

x

x

x

x

x

x

x

using the Master/Slave select when cascading more than

one device

M/S = H for

BUSY

output flag on Master,

M/S = L for

BUSY

input on Slave

Interrupt Flag

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

TTL-compatible, single 5V (鹵10%) power supply

Available in 68-pin PGA and PLCC and a 80-pin TQFP

Industrial temperature range (聳40擄C to +85擄C) is available

for selected speeds

Functional Block Diagram

OE

L

CE

L

R/W

L

OE

R

CE

R

R/W

R

I/O

0L

- I/O

7L

I/O

Control

BUSY

L

A

14L

A

0L

(1,2)

I/O

0R

-I/O

7R

I/O

Control

BUSY

R

A

14R

A

0R

(1,2)

Address

Decoder

15

MEMORY

ARRAY

15

Address

Decoder

CE

L

OE

L

R/W

L

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

CE

R

OE

R

R/W

R

SEM

L

(2)

INT

L

NOTES:

1. (MASTER):

BUSY

is output; (SLAVE):

BUSY

is input.

2.

BUSY

and

INT

outputs are non-tri-stated push-pull.

M/S

SEM

R

INT

R

(2)

2940 drw 01

JUNE 1999

1

DSC 2940/8

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