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IDT5V9955 Datasheet

  • IDT5V9955

  • 3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W

  • 11頁

  • IDT

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IDT5V9955
3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W
INDUSTRIAL TEMPERATURE RANGE
3.3V PROGRAMMABLE
SKEW DUAL PLL CLOCK
DRIVER TURBOCLOCK鈩?W
FEATURES:
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IDT5V9955
Ref input is 5V tolerant
8 pairs of programmable skew outputs
Two separate A and B banks for individual control
Low skew: 185ps same pair, 250ps same bank, 350ps both
banks
Selectable positive or negative edge synchronization on each
bank: excellent for DSP applications
Synchronous output enable on each bank
Input frequency: 2MHz to 200MHz
Output frequency: 6MHz to 200MHz
3-level inputs for skew and PLL range control
3-level inputs for feedback divide selection multiply / divide
ratios of (1-6, 8, 10, 12) / (2, 4)
PLL bypass for DC testing
External feedback, internal loop filter
12mA balanced drive outputs
Low Jitter: <100ps cycle-to-cycle
Power-down mode on each bank
Lock indicator on each bank
Available in BGA package
DESCRIPTION
The IDT5V9955 is a high fanout 3.3V PLL based clock driver intended
for high performance computing and data-communications applications. A
key feature of the programmable skew is the ability of outputs to lead or lag
the REF input signal. The IDT5V9955 has sixteen programmable skew
outputs in eight banks of 2. The two separate PLLs allow the user to
independently control A and B banks. Skew is controlled by 3-level input
signals that may be hard-wired to appropriate HIGH-MID-LOW levels.
The feedback input allows divide-by-functionality from 1 to 12 through
the use of the xDS[1:0] inputs. This provides the user with frequency
multiplication from 1 to 12 without using divided outputs for feedback.
When the xsOE pin is held low, all the xbank outputs are synchronously
enabled. However, if xsOE is held high, all the xbank outputs except x2Q0
and x2Q1 are synchronously disabled. The xLOCK is high when the
xbank PLL has achieved phase lock.
Furthermore, when xPE is held high, all the outputs are synchronized
with the positive edge of the REF clock input. When xPE is held low, all the
xbank outputs are synchronized with the negative edge of REF. The
IDT5V9955 has LVTTL outputs with 12mA balanced drive outputs.
FUNCTIONAL BLOCK DIAGRAM
A
LOCK
A
FS
A
PE
REF
APD
A
sOE
TEST
B
PE
B
FS
B
LOCK
BPD
BsOE
3
3
PLL
/N
3
3
ADS1:0
A1Q
0
A1Q
1
Skew
Select
3
A1F1:0
3
B1F1:0
3
BDS1:0
3
Skew
Select
A
FB
B
FB
3
/N
3
3
PLL
3
B1Q
0
B1Q
1
A2Q
0
A2Q
1
Skew
Select
3
A2F1:0
3
B2F1:0
3
3
Skew
Select
B2Q
0
B2Q
1
A3Q
0
A3Q
1
3
Skew
Select
A3F1:0
3
B3F1:0
3
3
Skew
Select
B3Q
0
B3Q
1
A4Q
0
A4Q
1
Skew
Select
3
A4F1:0
3
B4F1:0
3
3
Skew
Select
B4Q
0
B4Q
1
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
c
2002
Integrated Device Technology, Inc.
JUNE 2002
DSC 5974/9

IDT5V9955相關(guān)型號PDF文件下載

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