鈥?/div>
Ref input is 5V tolerant
4 pairs of programmable skew outputs
Low skew: 185ps same pair, 250ps all outputs
Selectable positive or negative edge synchronization:
Excellent for DSP applications
Synchronous output enable
Input frequency: 6MHz to 200MHz
Output frequency: 6MHz to 200MHz
2x, 4x, 1/2, and 1/4 outputs
3-level inputs for skew and PLL range control
PLL bypass for DC testing
External feedback, internal loop filter
12mA balanced drive outputs
Low Jitter: <100ps cycle-to-cycle
Available in TQFP package
IDT5V9950
DESCRIPTION:
The IDT5V9950 is a high fanout 3.3V PLL based clock driver intended
for high performance computing and data-communications applications. A
key feature of the programmable skew is the ability of outputs to lead or lag
the REF input signal. The IDT5V9950 has eight programmable skew
outputs in four banks of 2. Skew is controlled by 3-level input signals that
may be hard-wired to appropriate HIGH-MID-LOW levels.
When the
sOE
pin is held low, all the outputs are synchronously enabled.
However, if
sOE
is held high, all the outputs except 2Q0 and 2Q1 are
synchronously disabled.
Furthermore, when PE is held high, all the outputs are synchronized with
the positive edge of the REF clock input. When PE is held low, all the outputs
are synchronized with the negative edge of REF. The IDT5V9950 has
LVTTL outputs with 12mA balanced drive outputs.
FUNCTIONAL BLOCK DIAGRAM
sOE
Skew
Select
3
3
1F1:0
PE TEST
Skew
Select
3
PLL
FB
3
FS
3F1:0
Skew
Select
3
3
3
2F1:0
1Q
0
1Q
1
2Q
0
2Q
1
3
REF
3Q
0
3Q
1
Skew
Select
3
3
4F1:0
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
4Q
0
4Q
1
INDUSTRIAL TEMPERATURE RANGE
1
c
2002
Integrated Device Technology, Inc.
FEBRUARY 2002
DSC 5870/4