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IDT5V9352PRI Datasheet

  • IDT5V9352PRI

  • 3.3V/2.5V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER

  • 10頁

  • IDT

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IDT5V9352
3.3V/2.5V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER
INDUSTRIAL TEMPERATURE RANGE
3.3V/2.5V PHASE-LOCK
LOOP CLOCK DRIVER
ZERO DELAY BUFFER
FEATURES:
鈥?Phase-lock loop clock distribution for high performance clock
tree applications
鈥?Output enable bank control
鈥?External feedback (FBIN) pin is used to synchronize the
outputs to the clock input signal
鈥?No external RC network required for PLL loop stability
鈥?Operates at 3.3V/2.5V V
CC
鈥?Spread Spectrum Compatible
鈥?Operating frequency up to 200MHz
鈥?Compatible with Motorola MPC9352
鈥?Available in 32-pin TQFP package
IDT5V9352
DESCRIPTION:
The 5V9352 is a low-skew, low-jitter, phase-lock loop (PLL) clock driver
targeted for high performance clock tree applications. It uses a PLL to
precisely align, in both frequency and phase. The 5V9352 operates at 2.5V
and 3.3V.
The 5V9352 features three banks of individually configurable outputs.
The banks are configured with five, four, and two outputs. The internal
divide circuitry allows for output frequency ratios of 1:1, 2:1, 3:1, and 3:2:1.
The output frequency relationship is controlled by the f
SEL
frequency
control pins. The f
SEL
pins, as well as other inputs, are LVCMOS/LVTTL
compatible inputs
Unlike many products containing PLLs, the 5V9352 does not require
external RC networks. The loop filter for the PLL is included on-chip,
minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the 5V9352 requires a stabilization
time to achieve phase lock of the feedback signal to the reference signal.
This stabilization time is required, following power up and application of a
fixed-frequency, fixed-phase signal at REFCLK, as well as following any
changes to the PLL reference or feedback signals. The PLL can be
bypassed for test purposes by setting the
PLL_EN
to high.
The 5V9352 is available in Industrial temperature range (-40擄C to
+85擄C).
FUNCTIONAL BLOCK DIAGRAM
BANK A
CCLK
REFCLK
REF
PLL
FBIN
FB
梅2
Q
A
3
Q
A
0
1
梅2
1
梅6
1
Q
A
1
0
0
梅4
0
Q
A
2
VCO
PLL_En
Q
A
4
BANK B
Q
B
0
VCO_
SEL
1
Q
B
1
f
SELA
0
Q
B
2
Q
B
3
f
SELB
BANK C
1
f
SELC
0
Q
C
0
Q
C
1
MR/OE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
c
2003
Integrated Device Technology, Inc.
AUGUST 2003
DSC 5973/18

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