鈭?/div>
A: 25MHz to 167MHz
Available in TSSOP package
DESCRIPTION:
The IDT5V2528 is a high performance, low-skew, low-jitter, phase-lock
loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency
and phase, the feedback (FBOUT) output to the clock (CLK) input signal.
The IDT5V2528 inputs, PLL core, Y
0
, Y
1
, and FB
OUT
buffers operate from
the 3.3V V
DD
and AV
DD
power supply pins.
One bank of ten outputs provide low-skew, low-jitter copies of CLK. Of
the ten outputs, up to seven may be configured for 2.5V or 3.3V LVTTL
outputs. The number of 2.5V outputs is controlled by 3-level input signals
G_Ctrl and T_Ctrl, and by connecting the appropriate V
DDQ
pins to 2.5V or
3.3V. The 3-level input signals may be hard-wired to high-mid-low levels.
Output signal duty cycles are adjusted to 50 percent, independent of the duty
cycle at CLK. The outputs can be enabled or disabled via the G_Ctrl input.
When the G_Ctrl input is mid or high, the outputs switch in phase and
frequency with CLK; when the G_Ctrl is low, all outputs (except FB
OUT
) are
disabled to the logic-low state.
Unlike many products containing PLLs, the IDT5V2528 does not require
external RC networks. The loop filter for the PLL is included on-chip,
minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the IDT5V2528 requires a
stabilization time to achieve phase lock of the feedback signal to the
reference signal. This stabilization time is required, following power up and
application of a fixed-frequency, fixed-phase signal at CLK, as well as
following any changes to the PLL reference or feedback signals. The PLL
can be bypassed for test purposes by strapping AV
DD
to ground.
FUNCTIONAL BLOCK DIAGRAM
28
G_Ctrl
1
3
TY0, V
DDQ
pin 4
26
T_Ctrl
TY1, V
DDQ
pin 25
24
TY2, V
DDQ
pin 25
MODE
SELECT
17
TY3, V
DDQ
pin 15
16
TY4, V
DDQ
pin 15
13
TY5, V
DDQ
pin 11
12
TY6, V
DDQ
pin 11
CLK
6
PLL
10
TY7, V
DDQ
pin 11
20
Y0, V
DD
pin 21
19
FBIN
7
AV
DD
5
22
Y1, V
DD
pin 21
FBOUT, V
DD
pin 21
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
c
2002
Integrated Device Technology, Inc.
JUNE 2003
DSC 5971/11
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