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IDT5T93GL06 Datasheet

  • IDT5T93GL06

  • 2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER-TM II

  • 15頁

  • IDT

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IDT5T93GL06
2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER II
INDUSTRIAL TEMPERATURE RANGE
2.5V LVDS 1:6 GLITCHLESS
CLOCK BUFFER
TERABUFFER鈩?II
FEATURES:
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IDT5T93GL06
DESCRIPTION:
Guaranteed Low Skew < 25ps (max)
Very low duty cycle distortion < 100ps (max)
High speed propagation delay < 2ns (max)
Up to 800MHz operation
Glitchless input clock switching up to 650MHz
Selectable inputs
Hot insertable and over-voltage tolerant inputs
3.3V / 2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V),
CML, or LVDS input interface
Selectable differential inputs to six LVDS outputs
Power-down mode
2.5V V
DD
Available in VFQFPN package
APPLICATIONS:
鈥?Clock distribution
The IDT5T93GL06 2.5V differential clock buffer is a user-selectable differ-
ential input to six LVDS outputs . The fanout from a differential input to six LVDS
outputs reduces loading on the preceding driver and provides an efficient clock
distribution network. The IDT5T93GL06 can act as a translator from a differential
HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to
LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be used to
translate to LVDS outputs. The redundant input capability allows for a glitchless
change-over from a primary clock source to a secondary clock source up to
650MHz. Selectable inputs are controlled by SEL. During the switchover, the
output will disable low for up to three clock cycles of the previously-selected input
clock. The outputs will remain low for up to three clock cycles of the newly-
selected clock, after which the outputs will start from the newly-selected input.
A FSEL pin has been implemented to control the switchover in cases where a
clock source is absent or is driven to DC levels below the minimum specifications.
The IDT5T93GL06 outputs can be asynchronously enabled/disabled.
When disabled, the outputs will drive to the value selected by the GL pin. Multiple
power and grounds reduce noise.
FUNCTIONAL BLOCK DIAGRAM
GL
G
OUTPUT
CONTROL
Q1
Q1
PD
OUTPUT
CONTROL
Q2
Q2
A1
A1
1
OUTPUT
CONTROL
Q3
Q3
A2
A2
0
OUTPUT
CONTROL
Q4
Q4
SEL
FSEL
OUTPUT
CONTROL
Q5
Q5
OUTPUT
CONTROL
Q6
Q6
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
OCTOBER 2003
DSC-6183/8
漏 2003 Integrated Device Technology, Inc.

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