鈥?/div>
IDT5T9316
DESCRIPTION:
Guaranteed Low Skew < 25ps (max)
Very low duty cycle distortion < 125ps (max)
High speed propagation delay < 1.75ns (max)
Up to 1GHz operation
Selectable inputs
Hot insertable and over-voltage tolerant inputs
3.3V / 2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V),
CML, or LVDS input interface
Selectable differential inputs to sixteen LVDS outputs
Power-down mode
2.5V V
DD
Available in VFQFPN package
The IDT5T9316 2.5V differential clock buffer is a user-selectable differential
input to sixteen LVDS outputs. The fanout from a differential input to sixteen LVDS
outputs reduces loading on the preceding driver and provides an efficient clock
distribution network. The IDT5T9316 can act as a translator from a differential
HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to
LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be used to
translate to LVDS outputs. The redundant input capability allows for an
asynchronous change-over from a primary clock source to a secondary clock
source. Selectable reference inputs are controlled by SEL.
The IDT5T9316 outputs can be asynchronously enabled/disabled. When
disabled, the outputs will drive to the value selected by the GL pin. Multiple power
and grounds reduce noise.
APPLICATIONS:
鈥?Clock distribution
FUNCTIONAL BLOCK DIAGRAM
GL
G1
OUTPUT
CONTROL
Q1
Q1
OUTPUT
CONTROL
Q2
Q2
PD
OUTPUT
CONTROL
Q3
Q3
OUTPUT
CONTROL
Q4
Q4
OUTPUT
CONTROL
A1
A1
Q5
Q5
1
OUTPUT
CONTROL
Q6
Q6
A2
A2
0
OUTPUT
CONTROL
Q7
Q7
SEL
OUTPUT
CONTROL
Q8
Q8
G2
OUTPUT
CONTROL
Q9
Q9
OUTPUT
CONTROL
Q10
Q10
OUTPUT
CONTROL
Q11
Q11
OUTPUT
CONTROL
Q12
Q12
OUTPUT
CONTROL
Q13
Q13
OUTPUT
CONTROL
Q14
Q14
OUTPUT
CONTROL
Q15
Q15
OUTPUT
CONTROL
Q16
Q16
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
MARCH 2004
DSC-6174/14
漏 2004 Integrated Device Technology, Inc.