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IDT5T905 Datasheet

  • IDT5T905

  • 2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER

  • 17頁

  • IDT

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IDT5T905
2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER
INDUSTRIAL TEMPERATURE RANGE
2.5V SINGLE DATA RATE
1:5 CLOCK BUFFER
TERABUFFER鈩?/div>
FEATURES:
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
IDT5T905
DESCRIPTION:
Guaranteed Low Skew < 25ps (max)
Very low duty cycle distortion
High speed propagation delay < 2.5ns. (max)
Up to 250MHz operation
Very low CMOS power levels
1.5V V
DDQ
for HSTL interface
Hot insertable and over-voltage tolerant inputs
3-level inputs for selectable interface
Selectable HSTL, eHSTL, 1.8V / 2.5V LVTTL, or LVEPECL input
interface
鈥?Selectable differential or single-ended inputs and five single-
ended outputs
鈥?2.5V V
DD
鈥?Available in TSSOP package
The IDT5T905 2.5V single data rate (SDR) clock buffer is a user-selectable
single-ended or differential input to five single-ended outputs buffer built on
advanced metal CMOS technology. The SDR clock buffer fanout from a single
or differential input to five single-ended outputs reduces the loading on the
preceding driver and provides an efficient clock distribution network. The
IDT5T905 can act as a translator from a differential HSTL, eHSTL, 1.8V/2.5V
LVTTL, LVEPECL, or single-ended 1.8V/2.5V LVTTL input to HSTL, eHSTL,
1.8V/2.5V LVTTL outputs. Selectable interface is controlled by 3-level input
signals that may be hard-wired to appropriate high-mid-low levels. Multiple
power and grounds reduce noise.
鈥?Clock and signal distribution
APPLICATIONS:
FUNCTIONAL BLOCK DIAGRAM
TxS
GL
G
OUTPUT
CONTROL
Q
1
RxS
A
A/V
REF
OUTPUT
CONTROL
Q
2
OUTPUT
CONTROL
Q
3
OUTPUT
CONTROL
Q
4
OUTPUT
CONTROL
Q
5
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
FEBRUARY 2003
DSC-5942/25
漏 2003 Integrated Device Technology, Inc.

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