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IDT5T2110 Datasheet

  • IDT5T2110

  • 2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER TERACLOCK

  • 23頁

  • IDT

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IDT5T2110
2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER TERACLOCK
INDUSTRIAL TEMPERATURE RANGE
2.5V ZERO DELAY PLL
DIFFERENTIAL CLOCK
DRIVER TERACLOCK鈩?/div>
FEATURES:
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IDT5T2110
2.5 V
DD
6 differential outputs
Low skew: 100ps all outputs
Selectable positive or negative edge synchronization
Tolerant of spread spectrum input clock
Synchronous output enable
Selectable inputs
Input frequency: 4.17MHz to 250MHz
Output frequency: 12.5MHz to 250MHz
1.8V / 2.5V LVTTL: up to 250MHz
HSTL / eHSTL: up to 250MHz
Hot insertable and over-voltage tolerant inputs
3-level inputs for selectable interface
3-level inputs for feedback divide selection with multiply ratios
of(1-6, 8, 10, 12)
Selectable HSTL, eHSTL, 1.8V/2.5V LVTTL, or LVEPECL input
interface
Selectable differential or single-ended inputs and six differen-
tial outputs
PLL bypass for DC testing
External differential feedback, internal loop filter
Low Jitter: <75ps cycle-to-cycle
Power-down mode
Lock indicator
Available in BGA and VFQFPN package
DESCRIPTION:
The IDT5T2110 is a 2.5V PLL differential clock driver intended for high
performance computing and data-communications applications. The
IDT5T2110 has six differential outputs in six banks, including a dedicated
differential feedback. The redundant input capability allows for a smooth
change over to a secondary clock source when the primary clock source
is absent.
The feedback bank allows divide-by-functionality from 1 to 12 through
the use of the DS[1:0] inputs. This provides the user with frequency
multiplication 1 to 12 without using divided outputs for feedback. Each output
bank also allows for a divide-by functionality of 2 or 4.
The 5T2110 features a user-selectable, single-ended or differential input to
six differential outputs. The differential clock driver also acts as a translator from
a differential HSTL, eHSTL, 1.8V/2.5V LVTTL, LVEPECL, or single-ended
1.8V/2.5V LVTTL input to HSTL, eHSTL, or 1.8V/2.5V LVTTL outputs.
Selectable interface is controlled by 3-level input signals that may be hard-wired
to appropriate high-mid-low levels. The differential outputs can be synchro-
nously enabled/disabled.
Furthermore, when PE is held high, all the outputs are synchronized with
the positive edge of the REF clock input. When PE is held low, all the outputs
are synchronized with the negative edge of REF.
FUNCTIONAL BLOCK DIAGRAM
1sOE
OMODE
TxS
Divide
Select
1
Q
1
Q
1F
2:1
PD
PE
FS
LOCK
PLL_EN
FB
FB/
V
REF2
3
/N
3
PLL
0
3F
2:1
0
1
RxS
1
REF
1
REF
1
/
V
REF1
REF_SEL
4F
2:1
Divide
Select
Divide
Select
2F
2:1
Divide
Select
Divide
Select
2sOE
2
Q
2
Q
3sOE
3
Q
3
Q
DS
1:0
REF
0
REF
0
/
V
REF0
4sOE
4
Q
4
Q
5sOE
5
Q
5
Q
5F
2:1
Divide
Select
Q
FB
Q
FB
FBF
2:1
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
c
2004
Integrated Device Technology, Inc.
MAY 2003
DSC 5982/25

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