Power off disable outputs permit 鈥渓ive insertion鈥?/div>
Meets or exceeds JEDEC standard 18 specifications
Product available in Radiation Tolerant and Radiation
Enhanced versions
Military product compliant to MIL-STD-883, Class B
and DESC listed (dual marked)
Available in DIP, SOIC, QSOP, CERPACK and LCC
packages
DESCRIPTION:
The IDT54/74FCT377T/AT/CT/DT are octal D flip-flops built
using an advanced dual metal CMOS technology. The IDT54/
74FCT377T/AT/CT/DT have eight edge-triggered, D-type flip-
flops with individual D inputs and O outputs. The common
buffered Clock (CP) input loads all flip-flops simultaneously
when the Clock Enable (
CE
) is LOW. The register is fully
edge-triggered. The state of each D input, one set-up time
before the LOW-to-HIGH clock transition, is transferred to the
corresponding flip-flop鈥檚 O output. The
CE
input must be
stable only one set-up time prior to the LOW-to-HIGH transi-
tion for predictable operation.
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
FUNCTIONAL BLOCK DIAGRAM
D
0
CE
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D Q
CP
CP
O
0
D Q
CP
D Q
CP
D Q
CP
D Q
CP
D Q
CP
D Q
CP
D Q
CP
O
1
O
2
O
3
O
4
O
5
O
6
O
7
2630 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
漏1995
Integrated Device Technology, Inc.
APRIL 1995
DSC-4200/3
6.14
1
IDT54FCT377TSO相關型號PDF文件下載
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版本
描述
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英文版
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SINGLE OUTPUT CLOCK GENERATOR
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1
2
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