鈥?Power off disable outputs permit 鈥渓ive insertion鈥?/div>
鈥?Typical V
OLP
(Output Ground Bounce) < 1.0V at
V
CC
= 5V, T
A
= 25擄C
鈥?Features for FCT162841AT/BT/CT/ET:
鈥?Balanced Output Drivers:
鹵24mA
(commercial),
鹵16mA
(military)
鈥?Reduced system switching noise
鈥?Typical V
OLP
(Output Ground Bounce) < 0.6V at
V
CC
= 5V,T
A
= 25擄C
DESCRIPTION:
The FCT16841AT/BT/CT/ET and FCT162841AT/BT/CT/
ET 20-bit transparent D-type latches are built using advanced
dual metal CMOS technology. These high-speed, low-power
latches are ideal for temporary storage of data. They can be
used for implementing memory address latches, I/O ports,
and bus drivers. The Output Enable and Latch Enable controls
are organized to operate each device as two 10-bit latches or
one 20-bit latch. Flow-through organization of signal pins
simplifies layout. All inputs are designed with hysteresis for
improved noise margin.
The FCT16841AT/BT/CT/ET are ideally suited for driving
high-capacitance loads and low-impedance backplanes. The
output buffers are designed with power off disable capability
to allow "live insertion" of boards when used as backplane
drivers.
The FCT162841AT/BT/CT/ET have balanced output drive
with current limiting resistors. This offers low ground bounce,
minimal undershoot, and controlled output fall times鈥搑educing
the need for external series terminating resistors. The
FCT162841AT/BT/CT/ET are plug-in replacements for the
FCT16841AT/BT/CT/ET and ABT16841 for on-board inter-
face applications.
FUNCTIONAL BLOCK DIAGRAM
1
OE
2
OE
1
LE
1
D
1
2
LE
D
1
Q
1
2
D
1
D
2
Q
1
C
C
TO 9 OTHER CHANNELS
2556 drw 01
TO 9 OTHER CHANNELS
2556 drw 02
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
漏1996
Integrated Device Technology, Inc.
JULY 1996
DSC-2556/7
5.18
1