鈥?Power off disable outputs permit 鈥渓ive insertion鈥?/div>
鈥?Typical V
OLP
(Output Ground Bounce) < 1.0V at
V
CC
= 5V, T
A
= 25擄C
鈥?Features for FCT162240T/AT/CT/ET:
鈥?Balanced Output Drivers:
鹵24mA
(commercial),
鹵16mA
(military)
鈥?Reduced system switching noise
鈥?Typical V
OLP
(Output Ground Bounce) < 0.6V at
V
CC
= 5V,T
A
= 25擄C
DESCRIPTION:
The FCT16240T/AT/CT/ET and FCT162240T/AT/CT/ET
16-bit buffer/line drivers are built using advanced dual metal
CMOS technology. These high-speed, low-power devices
offer bus/backplane interface capability with improved packing
density. The flow-through organization of signal pins simplifies
layout. The three-state controls are designed to operate these
devices in a Quad-Nibble, Dual-Byte or single 16-bit word
mode. All inputs are designed with hysteresis for improved
noise margin.
The FCT16240T/AT/CT/ET are ideally suited for driving
high capacitance loads and low-impedance backplanes. The
output buffers are designed with power off disable capability
to allow "live insertion" of boards when used as backplane
drivers.
The FCT162240T/AT/CT/ET have balanced output drive
with current limiting resistors. This offers low ground bounce,
minimal undershoot, and controlled output fall times鈥?reduc-
ing the need for external series terminating resistors. The
FCT162240T/AT/CT/ET are plug-in replacements for
FCT16240T/AT/CT/ET and 54/74ABT16240 for on-board in-
terface applications.
FUNCTIONAL BLOCK DIAGRAM
1
OE
1
A
1
1
A
2
1
A
3
1
A
4
1
Y
1
1
Y
2
1
Y
3
1
Y
4
3
OE
3
A
1
3
A
2
3
A
3
3
A
4
3
Y
1
3
Y
2
3
Y
3
3
Y
4
2
OE
2
A
1
2
A
2
2
A
3
2
A
4
2
Y
1
2
Y
2
2
Y
3
2
Y
4
4
OE
4
A
1
4
A
2
4
A
3
4
A
4
4
Y
1
4
Y
2
4
Y
3
4
Y
4
2541 drw 02
2541 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
漏1996
Integrated Device Technology, Inc.
AUGUST 1996
DSC鈥?226/9
5.1
1
1
2
3
4
5
6
7
8
