82C82
March 1997
CMOS Octal Latching Bus Driver
Description
The Intersil 82C82 is a high performance CMOS Octal
Latching Buffer manufactured using a self-aligned silicon
gate CMOS process (Scaled SAJI IV). The 82C82 provides
an eight-bit parallel latch/buffer in a 20 pin package. The
active high strobe (STB) input allows transparent transfer of
data and latches data on the negative transition of this sig-
nal. The active low output enable (OE) permits simple inter-
face to state-of-the-art microprocessor systems.
Features
鈥?Full Eight-Bit Parallel Latching Buffer
鈥?Bipolar 8282 Compatible
鈥?Three-State Noninverting Outputs
鈥?Propagation Delay . . . . . . . . . . . . . . . . . . . . . 35ns Max.
鈥?Gated Inputs:
- Reduce Operating Power
- Eliminate the Need for Pull-Up Resistors
鈥?Single 5V Power Supply
鈥?Low Power Operation . . . . . . . . . . . . . . . ICCSB = 10碌A
鈥?Operating Temperature Ranges
- C82C82 . . . . . . . . . . . . . . . . . . . . . . . . . .0
o
C to +70
o
C
- I82C82 . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to +85
o
C
- M82C82 . . . . . . . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Ordering Information
PART NUMBER
CP82C82
IP82C82
CS82C82
IS82C82
CD82C82
ID82C82
MD82C82/B
8406701RA
MR82C82/B
84067012A
TEMP. RANGE
0
o
C to +70
o
C
-40
o
C to +85
o
C
0
o
C to +70
o
C
-40
o
C to +85
o
C
0
o
C to +70
o
C
-40
o
C to +85
o
C
-55
o
C to +125
o
C
SMD #
-55
o
C to +125
o
C 20 Pad CLCC
SMD #
J20.A
20 Ld CERDIP F20.3
20 Ld PLCC
N20.35
PACKAGE
20 Ld PDIP
PKG. NO.
E20.3
Pinouts
82C82 (PDIP, CERDIP)
TOP VIEW
82C82 (PLCC, CLCC)
TOP VIEW
DI
2
DI
1
DI
0
DO
0
V
CC
STB
X
H
H
DI
3
4
DI
4
5
DI
5
6
DI
6
7
DI
7
8
18 DO
1
17 DO
2
16 DO
3
15 DO
4
14 DO
5
H
L
X
鈥?/div>
鈫?/div>
TRUTH TABLE
OE
H
L
L
L
DI
X
L
H
X
DO
Hi-Z
L
H
鈥?/div>
3
DI
0
DI
1
DI
2
DI
3
DI
4
DI
5
DI
6
DI
7
OE
1
2
3
4
5
6
7
8
9
20 V
CC
19 DO
0
18 DO
1
17 DO
2
16 DO
3
15 DO
4
14 DO
5
13 DO
6
12 DO
7
11 STB
2
1
20
19
= Logic One
= Logic Zero
= Don鈥檛 Care
= Latched to Value of Last
Data
Hi-Z = High Impedance
鈫?/div>
= Neg. Transition
PIN NAMES
9
OE
10
GND
11
STB
12
DO
7
13
DO
6
GND 10
PIN
DI
0
-DI
7
DO
0
-DO
7
STB
OE
DESCRIPTION
Data Input Pins
Data Output Pins
Active High Strobe
Active Low Output
Enable
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
漏
Intersil Corporation 1999
File Number
2975.1
4-274
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