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ID82C284 Datasheet

  • ID82C284

  • Clock Generator and Ready Interface for 80C286 Processors

  • 75.65KB

  • 11頁(yè)

  • INTERSIL   INTERSIL

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82C284
March 1997
Clock Generator and Ready Interface
for 80C286 Processors
Description
The Intersil 82C284 is a clock generator/driver which
provides clock signals for 80C286 processors and support
components. It also contains logic to supply READY to the
CPU from either asynchronous or synchronous sources and
synchronous RESET from an asynchronous input with
hysteresis.
Features
鈥?Generates System Clock for 80C286 Processors
鈥?Generates System Reset Output from Schmitt
Trigger Input
- Improved Hysteresis
鈥?Uses Crystal or External Signal for Frequency Source
鈥?Dynamically Switchable between Two Input
Frequencies
鈥?Provides Local READY and MULTIBUS
廬
READY
Synchronization
鈥?Static CMOS Technology
鈥?Single +5V Power Supply
鈥?Available in 18 Lead CerDIP Package
Ordering Information
PART NUMBER
CD82C284-12
ID82C284-10
ID82C284-12
TEMP. RANGE
0
o
C to +70
o
C
-40
o
C to +85
o
C
-40
o
C to +85
o
C
PACKAGE
PKG.
NO.
18 Ld CERDIP F18.3
18 Ld CERDIP F18.3
18 Ld CERDIP F18.3
Pinout
82C284 (CERDIP)
TOP VIEW
Functional Diagram
RESET
ARDY
SRDY
SRDYEN
READY
EFI
F/C
X1
X2
GND
1
2
3
4
5
6
7
8
9
18 VCC
17 ARDYEN
16 S1
15 S0
14 NC
13 PCLK
12 RESET
11 RES
10 CLK
EFI
F/C
ARDYEN
ARDY
X1
X2
XTAL
OSC
MUX
RES
SYNCHRONIZER
RESET
CLK
SYNCHRONIZER
SRDYEN
SRDY
READY LOGIC
READY
S1
S0
PCLK GENERATOR
PCLK
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
漏
Intersil Corporation 1999
MULTIBUS
File Number
2966.1
廬
is a patented Intel bus.
1

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