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ICS95420YGLFT Datasheet

  • ICS95420YGLFT

  • Programmable Timing Control HubTM for Mobile P4TM Systems

  • 16頁

  • ICS

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Integrated
Circuit
Systems, Inc.
ICS954204
Programmable Timing Control Hub鈩?for Mobile P4鈩?Systems
Recommended Application:
CK410M Compliant Main Clock with Integrated LCD Spread
Spectrum Clock.
Output Features:
鈥?/div>
2 - 0.7V current-mode differential CPU pairs
鈥?/div>
5 - 0.7V current-mode differential SRC pair for SATA and
PCI-E
鈥?/div>
1 - 0.7V current-mode differential CPU/SRC selectable
pair
鈥?/div>
4 - PCI (33MHz)
鈥?/div>
2 - PCICLK_F, (33MHz) free-running
鈥?/div>
1 - USB, 48MHz
鈥?/div>
1 - DOT, 96MHz, 0.7V current differential pair
鈥?/div>
1 - REF, 14.318MHz
鈥?/div>
1 - 0.7V current-mode differential LCD/SRC selectable
pair.
Key Specifications:
鈥?/div>
CPU outputs cycle-cycle jitter < 85ps
鈥?/div>
SRC outputs cycle-cycle jitter < 125ps
鈥?/div>
PCI outputs cycle-cycle jitter < 500ps
鈥?/div>
+/- 300ppm frequency accuracy on CPU & SRC clocks
鈥?/div>
+/- 100ppm frequency accuracy on USB clocks
Features/Benefits:
鈥?/div>
Supports tight ppm accuracy clocks for Serial-ATA and
SRC
鈥?/div>
Supports programmable spread percentage and
frequency
鈥?/div>
鈥?/div>
鈥?/div>
Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
Supports undriven differential CPU, SRC pair in PD#
for power management.
CLKREQ pins to support SRC power management.
Pin Configuration
VDDPCI
GND
PCICLK3
PCICLK4
PCICLK5
GND
VDDPCI
ITP_EN/PCICLK_F0
*SELSRC_LCDCLK#/PCICLK_F1
Vtt_PwrGd#/PD
VDD48
FS
L
A/USB_48MHz
GND
DOTT_96MHz
DOTC_96MHz
FS
L
B/TEST_MODE
LCDCLK_SST/SRCCLKT0
LCDCLK_SSC/SRCCLKC0
SRCCLKT1
SRCCLKC1
VDDSRC
SRCCLKT2
SRCCLKC2
SRCCLKT3
SRCCLKC3
SRCCLKT4_SATA
SRCCLKC4_SATA
VDDSRC
Functionality
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PCICLK2
PCI/SRC_STOP#
CPU_STOP#
FS
L
C/TEST_SEL
REFOUT
GND
X1
X2
VDDREF
SDATA
SCLK
GND
CPUCLKT0
CPUCLKC0
VDDCPU
CPUCLKT1
FS_C FS_B FS_A
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
CPU
MHz
266.67
133.33
200.00
166.67
333.33
100.00
400.00
200.00
SRC
MHz
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
PCI
MHz
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
REF
MHz
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
U
SB
MHz
48.00
48.00
48.00
48.00
48.00
48.00
48.00
48.00
DOT
MHz
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
ICS954204
1. FS_C is a three-level input. Please see V
IL_FS
and V
IH_FS
specifications in the
Input/Supply/Common Output Parameters Table for correct values. Also refer
to the Test Clarification Table.
2. FS_B and FS_A are low-threshold inputs. Please see the V
IL_FS
and V
IH_FS
CPUCLKC1
specifications in the Input/Supply/Common Output Parameters Table for
IREF
correct values.
GNDA
VDDA
CPUCLKT2_ITP/SRCCLKT7
CPUCLKC2_ITP/SRCCLKC7
VDDSRC
CLKREQA#*
CLKREQB#*
SRCCLKT5
SRCCLKC5
GND
56-pin TSSOP
*100Kohm Pull-Up Resistor
0933D鈥?3/16/05

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