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ICS954201YFLNT Datasheet

  • ICS954201YFLNT

  • Programmable Timing Control Hub⑩ for Mobile P4⑩ Systems

  • 15頁

  • ICS

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Integrated
Circuit
Systems, Inc.
ICS954201
Programmable Timing Control Hub鈩?for Mobile P4鈩?Systems
Recommended Application:
CK410M clock, Intel Yellow Cover part
Output Features:
鈥?/div>
2 - 0.7V current-mode differential CPU pairs
鈥?/div>
7 - 0.7V current-mode differential SRC pair for SATA and
PCI-E
鈥?/div>
1 - 0.7V current-mode differential CPU/SRC selectable
pair
鈥?/div>
4 - PCI (33MHz)
鈥?/div>
2 - PCICLK_F, (33MHz) free-running
鈥?/div>
1 - USB, 48MHz
鈥?/div>
1 - DOT, 96MHz, 0.7V current differential pair
鈥?/div>
1 - REF, 14.318MHz
Key Specifications:
鈥?/div>
CPU outputs cycle-cycle jitter < 85ps
鈥?/div>
SRC outputs cycle-cycle jitter < 125ps
鈥?/div>
PCI outputs cycle-cycle jitter < 500ps
鈥?/div>
+/- 300ppm frequency accuracy on CPU & SRC clocks
鈥?/div>
+/- 100ppm frequency accuracy on USB clocks
Pin Configuration
VDDPCI
GND
PCICLK3
PCICLK4
PCICLK5
GND
VDDPCI
ITP_EN/PCICLK_F0
PCICLK_F1
Vtt_PwrGd#/PD
VDD48
USB_48MHz/FS_A
GND
DOTT_96MHz
DOTC_96MHz
FS_B/TEST_MODE
SRCCLKT0
SRCCLKC0
SRCCLKT1
SRCCLKC1
VDDSRC
SRCCLKT2
SRCCLKC2
SRCCLKT3
SRCCLKC3
SRCCLKT4_SATA
SRCCLKC4_SATA
VDDSRC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PCICLK2
PCI/SRC_STOP#
CPU_STOP#
FS_C/TEST_SEL
REFOUT
GND
X1
X2
VDDREF
SDATA
1.
SCLK
GND
2.
CPUCLKT0
CPUCLKC0
VDDCPU
CPUCLKT1
CPUCLKC1
IREF
GNDA
VDDA
CPUCLKT2_ITP/SRCCLKT7
CPUCLKC2_ITP/SRCCLKC7
VDDSRC
SRCCLKT6
SRCCLKC6
SRCCLKT5
SRCCLKC5
GND
Features/Benefits:
鈥?/div>
Supports tight ppm accuracy clocks for Serial-ATA and
PCI-Express
鈥?/div>
Supports spread spectrum modulation, 0 to -0.5%
down spread
鈥?/div>
鈥?/div>
鈥?/div>
Supports CPU clocks up to 400MHz
Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
Supports undriven differential CPU, SRC pair in PD#
for power management.
Functionality
FS_C
0
0
0
0
1
1
1
1
1
FS_B FS_A
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
2
CPU
SRC
MHz
MHz
266.66
100.00
133.33
100.00
200.00
100.00
166.66
100.00
333.33
100.00
100.00
100.00
400.00
100.00
RESERVED
PCI
MHz
33.33
33.33
33.33
33.33
33.33
33.33
33.33
REF
MHz
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
U
SB
MHz
48.00
48.00
48.00
48.00
48.00
48.00
48.00
48.00
DOT
MHz
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
FS_C is a three-level input. Please see V
IL_FS
and V
IH_FS
specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
FS_B and FS_A are low-threshold inputs. Please see the V
IL_FS
and V
IH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
56-pin SSOP & TSSOP
0819G鈥?2/06/04
ICS954201

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