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ICS952607YFLF-T Datasheet

  • ICS952607YFLF-T

  • Programmable Timing Control Hub for Next Gen P4 processor

  • 21頁(yè)

  • ICS

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Integrated
Circuit
Systems, Inc.
ICS952607
Advance Information
Programmable Timing Control Hub鈩?for Next Gen P4鈩?processor
Recommended Application:
CK409 Compliant clock for Next Gen P4 Processor
Output Features:
鈥?/div>
2 - 0.7V current-mode differential CPU pairs
鈥?/div>
1 - 0.7V current-mode differential SRC pair
鈥?/div>
9 - PCI, 3 free running, 33MHz
鈥?/div>
3 - REF, 14.318MHz
鈥?/div>
3 - 3V66, 66.66MHz
鈥?/div>
1 - VCH/3V66, selectable 48MHz or 66MHz
鈥?/div>
2 - 48MHz
鈥?/div>
1 - 24/48MHz
Key Specifications:
鈥?/div>
CPU/SRC outputs cycle-cycle jitter < 125ps
鈥?/div>
3V66 outputs cycle-cycle jitter < 250ps
鈥?/div>
PCI outputs cycle-cycle jitter < 250ps
鈥?/div>
+/- 300ppm frequency accuracy on CPU & SRC clocks
Features/Benefits:
鈥?/div>
QuadRom
TM
frequency selection.
鈥?/div>
Programmable output frequency.
鈥?/div>
Programmable asynchronous 3V66&PCI frequency.
鈥?/div>
Programmable output divider ratios.
鈥?/div>
Programmable output rise/fall time.
鈥?/div>
Programmable output skew.
鈥?/div>
Programmable spread percentage for EMI control.
鈥?/div>
Watchdog timer technology to reset system if system
malfunctions.
鈥?/div>
Programmable watch dog safe frequency.
鈥?/div>
Support I2C Index read/write and block read/write
operations.
鈥?/div>
Uses external 14.318MHz reference input.
鈥?/div>
Supports tight ppm accuracy clocks for Serial-ATA
鈥?/div>
Supports spread spectrum modulation, 0 to -0.5%
down spread and +/- 0.25% center spread
鈥?/div>
Supports CPU clks up to 400MHz
Functionality
Bit4 Bit3 Bit2 Bit1 Bit0 CPU
FS4 FS3 FS2 FS1 FS0 MHz
100.00
0
0
0
0
0
200.00
0
0
0
0
1
133.33
0
0
0
1
0
166.67
0
0
0
1
1
0
0
1
0
0
200.00
0
0
1
0
1
400.00
0
0
1
1
0
266.67
0
0
1
1
1
333.33
100.99
0
1
0
0
0
201.98
0
1
0
0
1
134.65
0
1
0
1
0
168.31
0
1
0
1
1
1
115.00
0
1
0
0
230.00
0
1
1
0
1
153.33
0
1
1
1
0
191.67
0
1
1
1
1
1
100.00
0
0
0
0
200.00
1
0
0
0
1
133.33
1
0
0
1
0
166.67
1
0
0
1
1
0
1
0
0
200.00
1
400.00
1
0
1
0
1
266.67
1
0
1
1
0
333.33
1
0
1
1
1
105.00
1
1
0
0
0
210.00
1
1
0
0
1
140.00
1
1
0
1
0
175.00
1
1
0
1
1
1
110.00
1
1
0
0
220.00
1
1
1
0
1
146.66
1
1
1
1
0
1
1
1
1
1
183.34
0734鈥?7/16/04
Pin Configuration
AGP
MHz
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
67.33
67.33
67.33
67.32
76.66
76.66
76.66
76.66
66.66
66.66
66.66
71.43
66.66
66.66
66.66
66.66
69.99
69.99
69.99
69.99
73.33
73.33
73.33
73.33
PCI
MHz
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.66
33.66
33.66
33.66
38.33
38.33
38.33
38.33
33.33
33.33
33.33
35.71
33.33
33.33
33.33
33.33
35.00
35.00
35.00
35.00
36.66
36.66
36.66
36.66
*FS1/REF0 1
48 VDDA
*FS0/REF1 2
47 GND
REF2 3
46 IREF
VDDREF 4
45 Reset#
X1 5
44 GND
X2 6
43 CPUCLKT1
GND 7
42 CPUCLKC1
**FS2/PCICLK_F0 8
41 VDDCPU
**FS4/PCICLK_F1 9
40 CPUCLKT0
PCICLK_F2 10
39 CPUCLKC0
11
38 GND
VDDPCI
37 SRCCLKT
GND 12
36 SRCCLKC
^^PCICLK0 13
14
35 VDD
PCICLK1
34 VttPWR_GD/PD#
PCICLK2 15
33 SDATA
PCICLK3 16
32 SCLK
VDDPCI 17
31 3V66_0
GND 18
19
30 3V66_1
PCICLK4
29 GND
PCICLK5 20
**Sel24_48#/24_48MHz 21
28 VDD3V66
22
27 3V66_2
**FS3/48MHz_0
26 3V66_3/VCH
48MHz_1 23
24
25 VDD48
GND
* This pin have 120K pull-up to VDD
** This pin have 120K pull-down to GND
^^ An external 2.2K pull-down resistor is needed on this pin
ICS952607
48-pin SSOP
Note: FS1 and FS0 are equal to Intel CK409-defined FSA and FSB,
respectively.
ADVANCE INFORMATION
documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.

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