鈥?/div>
PCI outputs cycle-cycle jitter < 250ps
CPU outputs skew: < 100ps
+/- 300ppm frequency accuracy on CPU & SRC clocks
Pin Configuration
Functionality
U
SB/
FS2
CPU
SRC
3V66
PCI
REF
DOT
MHz
B6b5 FS_A FS_B MHz
MHz
MHz MHz
MHz
0
0
100.00 100/200 66.66 33.33 14.318 48.00
0
1
200.00 100/200 66.66 33.33 14.318 48.00
0
1
0
133.33 100/200 66.66 33.33 14.318 48.00
1
1
166.66 100/200 66.66 33.33 14.318 48.00
0
0
200.00 100/200 66.66 33.33 14.318 48.00
0
1
400.00 100/200 66.66 33.33 14.318 48.00
1
1
0
266.66 100/200 66.66 33.33 14.318 48.00
1
1
333.33 100/200 66.66 33.33 14.318 48.00
*FSA/REF0
*FSB/REF1
VDDREF
X1
X2
GND
PCICLK_F0
PCICLK_F1
PCICLK_F2
VDDPCI
GND
PCICLK0
PCICLK1
PCICLK2
PCICLK3
VDDPCI
GND
PCICLK4
PCICLK5
PD#
48MHz_DOT
48MHz_USB
GND
VDD48
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDA
GND
IREF
CPUCLKT_ITP
CPUCLKC_ITP
GND
CPUCLKT1
CPUCLKC1
VDDCPU
CPUCLKT0
CPUCLKC0
GND
SRCCLKT
SRCCLKC
VDD
Vtt_Pwrgd#
SDATA
SCLK
3V66_0
3V66_1
GND
VDD3V66
3V66_2
3V66_3/VCH
**120KW pull-down
48-pin SSOP
0717F鈥?6/10/05
ICS952606