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ICS952301YG-T Datasheet

  • ICS952301YG-T

  • Frequency Timing Generator for Transmeta Systems

  • 12頁(yè)

  • ICS

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Integrated
Circuit
Systems, Inc.
ICS952301
Advance Information
Frequency Timing Generator for Transmeta Systems
Recommended Application:
Transmeta
Output Features:
鈥?1CPU up to 66.6MHz &
overclocking of 66MHz.
鈥?7 PCI (3.3V) @ 33.3MHz (all are free running
selectable) w/ 2 selectable 1X/2X.
鈥?/div>
鈥?/div>
鈥?/div>
1 REF (3.3V) at 14.318MHz.
1 48MHz (3.3V).
1 24_48MHz selectable output.
Pin Configuration
GNDREF
X1
X2
PD#
PCICLK0
PCICLK1
GNDPCI
VDDPCI
PCICLK2
1
PCICLK3
PCICLK4
1
GNDPCI
VDDPCI
PCICLK5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDDREF
REF/ 1X or 2X Programmable
*
CPU_STOP#
VDDCPU/CORE
GNDCPU/CORE
CPUCLK0
PCI_STOP#
SCLK
VDD48
GND48
48MHz
24-48MHz/Sel 48_24#
*
SDATA
PCICLK6
Features:
鈥?Supports Spread Spectrum modulation for CPU and
PCI clocks, default -2.0% downspread.
鈥?Efficient Power management scheme through stop
clocks and power down modes.
鈥?Uses external 14.318MHz crystal, no external load
cap required for CL=18pF crystal.
鈥?28-pin TSSOP package, 4.40mm (173mil).
Skew Characteristics:
鈥?PCI 鈥?PCI < 500ps
鈥?CPU(early) 鈥?PCI = 1.5ns 鈥?4ns.
28-Pin 173mil TSSOP
Note: ^ Internal Pulldown Resistor
* Internal Pullup Resistor
1 1X/2X Programmable
Block Diagram
X1
X2
XTAL
OSC
REF
STOP
CPU
CPU
PLL
PCI DIV
STOP
PCI(6:0)
SCLOCK
SDATA
PD#
PCI_STOP#
SEL48_24#
CPU_STOP#
Control
Logic
48MHz
PLL
STOP
48MHz
Power Groups
VDD_Core, GND_Core = PLL core
VDDREF, GNDREF = REF, X1, X2
VDDPCI, GNDPCI = PCICLK (6:0)
VDD48, GND48 = 48MHz (1:0)
Pentium is a trademark on Intel Corporation.
24/48
STOP
24/48MHz
0673鈥?7/09/02
ADVANCE INFORMATION
documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
952301AG

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