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ICS952004 Datasheet

  • ICS952004

  • Programmable Timing Control Hub⑩ for P4⑩ processor

  • 19頁

  • ICS

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Integrated
Circuit
Systems, Inc.
ICS952004
Programmable Timing Control Hub鈩?for P4鈩?processor
Recommended Application:
SIS 645/650 style chipsets.
Output Features:
鈥?/div>
2 - Pairs of differential CPUCLKs (differential current mode)
鈥?/div>
1 - SDRAM @ 3.3V
鈥?/div>
8 - PCI @3.3V
鈥?/div>
2 - AGP @ 3.3V
鈥?/div>
2 - ZCLKs @ 3.3V
鈥?/div>
1- 48MHz, @3.3V fixed.
鈥?/div>
1- 24/48MHz, @3.3V selectable by I
2
C
(Default is 24MHz)
鈥?/div>
3- REF @3.3V, 14.318MHz.
Features/Benefits:
鈥?/div>
Selectable asynchronous/synchronous AGP, ZCLK and
PCI outputs
鈥?/div>
Programmable output frequency, divider ratios, output rise/
falltime, output skew.
鈥?/div>
Programmable spread percentage for EMI control.
鈥?/div>
Watchdog timer technology to reset system
if system malfunctions.
鈥?/div>
Programmable watch dog safe frequency.
鈥?/div>
Support I
2
C Index read/write and block read/write
operations.
鈥?/div>
For PC133 SDRAM system use the ICS9179-16 as the
memory buffer.
鈥?/div>
For DDR SDRAM system use the ICS93705 or
ICS93722 as the memory buffer.
鈥?/div>
Uses external 14.318MHz crystal.
Key Specifications:
鈥?/div>
PCI - PCI output skew: < 500ps
鈥?/div>
CPU - SDRAM output skew: < 1ns
鈥?/div>
AGP - AGP output skew: <150ps
Pin Configuration
VDDREF
**FS0/REF0
**FS1/REF1
**FS2/REF2
GNDREF
X1
X2
GNDZ
ZCLK0
ZCLK1
VDDZ
*PCI_STOP#
VDDPCI
**FS3/PCICLK_F0
**FS4/PCICLK_F1
PCICLK0
PCICLK1
GNDPCI
VDDPCI
PCICLK2
PCICLK3
PCICLK4
PCICLK5
GNDPCI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDSD
SDRAM
GNDSD
CPU_STOP#*
CPUCLKT_1
CPUCLKC_1
VDDCPU
GNDCPU
CPUCLKT_0
CPUCLKC_0
IREF
GNDA
VDDA
SCLK
SDATA
PD#*/Vtt_PWRGD
GNDAGP
AGPCLK0
AGPCLK1
VDDAGP
VDDA48
48MHz
24_48MHz/MULTISEL*
GND48
48-Pin 300-mil SSOP
* These inputs have a 120K pull up to VDD.
** These inputs have a 120K pull down to GND.
Block Diagram
PLL2
/2
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
48MHz
24_48MHz
ICS952004
2
REF (1:0)
CPU
DIVDER
Stop
2
2
CPUCLKT (1:0)
CPUCLKC (1:0)
Functionality
Bit 2 Bit 7 Bit 6 Bit 5 Bit 4
CPU
SDRAM ZCLK
(MHz)
66.67
66.67
66.67
66.67
60.00
62.50
66.67
80.00
66.67
62.50
71.43
66.67
66.67
63.33
63.33
50.00
AGP
(MHz)
66.67
66.67
66.67
66.67
60.00
62.50
66.67
66.67
66.67
62.50
83.33
66.67
66.67
63.33
63.33
50.00
PCI
(MHz)
33.33
33.33
33.33
33.33
30.00
31.25
33.33
33.33
33.33
31.25
41.67
33.33
33.33
31.67
31.67
25.00
FS4 FS3 FS2 FS1 FS0 (MHz) (MHz)
0
0
0
0
0
66.67
66.67
0
0
0
0
1 100.00 100.00
0
0
0
1
0 100.00 200.00
0
0
0
1
1 100.00 133.33
0
0
1
0
0 100.00 150.00
0
0
1
0
1 100.00 125.00
0
0
1
1
0 100.00 160.00
0
0
1
1
1 100.00 133.33
0
1
0
0
0 100.00 200.00
0
1
0
0
1 100.00 166.67
0
1
0
1
0 100.00 166.67
0
1
0
1
1
80.00 133.33
0
1
1
0
0
80.00 133.33
0
1
1
0
1
95.00
95.00
0
1
1
1
0
95.00 126.67
0
1
1
1
1
66.67
66.67
SDATA
SCLK
FS (4:0)
PD#
PCI_STOP#
CPU_STOP#
MULTISEL
PD#/Vtt_PWRGD
Control
Logic
ZCLK
DIVDER
ZCLK (1:0)
2
PCI
DIVDER
Stop
6
PCICLK (9:0)
PCICLK_F (1:0)
2
AGP
DIVDER
2
AGP (1:0)
Config.
Reg.
SDRAM
DIVDER
SDRAM
I REF
Power Groups
VDDCPU = CPU
VDDPCI = PCICLK_F, PCICLK
VDDSD = SDRAM
AVDD48 = 48MHz, 24MHz, fixed PLL
AVDD = Analog Core PLL
VDDAGP= AGP
VDDREF = Xtal, REF
VDDZ = ZCLK
Note: For additional margin testing frequencies, refer to Byte 4
0489C鈥?2/10/04

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