音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

ICS952001 Datasheet

  • ICS952001

  • Preliminary Product Previes

  • 17頁

  • ICS

掃碼查看芯片數(shù)據(jù)手冊

上傳產(chǎn)品規(guī)格書

PDF預覽

Integrated
Circuit
Systems, Inc.
ICS952001
Preliminary Product Preview
Programmable Timing Control Hub聶 for P4聶 processor
Recommended Application:
SIS 645/650 style chipsets.
Output Features:
鈥?/div>
2 - Pairs of differential CPUCLKs (differential current mode)
鈥?/div>
1 - SDRAM @ 3.3V
鈥?/div>
8 - PCI @3.3V
鈥?/div>
2 - AGP @ 3.3V
鈥?/div>
2 - ZCLKs @ 3.3V
鈥?/div>
1- 48MHz, @3.3V fixed.
鈥?/div>
1- 24/48MHz, @3.3V selectable by I
2
C
(Default is 24MHz)
鈥?/div>
3- REF @3.3V, 14.318MHz.
Features/Benefits:
鈥?/div>
Programmable output frequency, divider ratios, output
rise/falltime, output skew.
鈥?/div>
Programmable spread percentage for EMI control.
鈥?/div>
Watchdog timer technology to reset system
if system malfunctions.
鈥?/div>
Programmable watch dog safe frequency.
鈥?/div>
Support I
2
C Index read/write and block read/write
operations.
鈥?/div>
For PC133 SDRAM system use the ICS9179-06 as the
memory buffer.
鈥?/div>
For DDR SDRAM system use the ICS93705 or
ICS93722 as the memory buffer.
鈥?/div>
Uses external 14.318MHz crystal.
Key Specifications:
鈥?/div>
PCI - PCI output skew: < 500ps
鈥?/div>
CPU - SDRAM output skew: < 1ns
鈥?/div>
AGP - AGP output skew: <150ps
Pin Configuration
VDDREF
**FS0/REF0
**FS1/REF1
**FS2/REF2
GNDREF
X1
X2
GNDZ
ZCLK0
ZCLK1
VDDZ
*PCI_STOP#
VDDPCI
**FS3/PCICLK_F0
**FS4/PCICLK_F1
PCICLK0
PCICLK1
GNDPCI
VDDPCI
PCICLK2
PCICLK3
PCICLK4
PCICLK5
GNDPCI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDSD
SDRAM
GNDSD
CPU_STOP#*
CPUCLKT_1
CPUCLKC_1
VDDCPU
GNDCPU
CPUCLKT_0
CPUCLKC_0
IREF
GNDA
VDDA
SCLK
SDATA
PD#*/Vtt_PWRGD
GNDAGP
AGPCLK0
AGPCLK1
VDDAGP
VDDA48
48MHz
24_48MHz/MULTISEL*
GND48
48-Pin 300-mil SSOP and TSSOP
* These inputs have a 120K pull up to VDD.
** These inputs have a 120K pull down to GND.
Block Diagram
PLL2
/2
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
48MHz
24_48MHz
ICS952001
2
REF (1:0)
Functionality
B it 2 B it 7 B it 6 B it 5 B it 4
FS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPU
(M H z )
6 6 .6 7
1 0 0 .0 0
1 0 0 .0 0
1 0 0 .0 0
1 0 0 .0 0
1 0 0 .0 0
1 0 0 .0 0
1 0 0 .0 0
1 0 0 .0 0
1 0 0 .0 0
1 0 0 .0 0
8 0 .0 0
8 0 .0 0
9 5 .0 0
9 5 .0 0
6 6 .6 7
SDRA M
(M H z )
6 6 .6 7
100.00
200.00
133.33
150.00
125.00
160.00
133.33
200.00
166.67
166.67
133.33
133.33
9 5 .0 0
126.67
6 6 .6 7
Z CLK
(M H z )
6 6 .6 7
6 6 .6 7
6 6 .6 7
6 6 .6 7
6 0 .0 0
6 2 .5 0
6 6 .6 7
8 0 .0 0
6 6 .6 7
6 2 .5 0
7 1 .4 3
6 6 .6 7
6 6 .6 7
6 3 .3 3
6 3 .3 3
5 0 .0 0
AGP
(M H z )
66.67
66.67
66.67
66.67
60.00
62.50
66.67
66.67
66.67
62.50
83.33
66.67
66.67
63.33
63.33
50.00
SDATA
SCLK
FS (4:0)
PD#
PCI_STOP#
CPU_STOP#
MULTISEL
PD#/Vtt_PWRGD
CPU
DIVDER
Stop
2
2
CPUCLKT (1:0)
CPUCLKC (1:0)
Control
Logic
ZCLK
DIVDER
ZCLK (1:0)
2
PCI
DIVDER
Stop
6
PCICLK (9:0)
PCICLK_F (1:0)
Config.
Reg.
2
AGP
DIVDER
2
AGP (1:0)
I REF
Power Groups
VDDCPU = CPU
VDDPCI = PCICLK_F, PCICLK
VDDSD = SDRAM
AVDD48 = 48MHz, 24MHz, fixed PLL
AVDD = Analog Core PLL
VDDAGP= AGP
VDDREF = Xtal, REF
VDDZ = ZCLK
Note: For additional margin testing frequencies, refer to Byte 4
952001 Rev A 01/24/02

ICS952001相關型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    32 KhZ Motherboard Frequency Generator
    ICS
  • 英文版
    32 KhZ Motherboard Frequency Generator
    ICST [Inte...
  • 英文版
    High Frequency System Clock Generator
    ICS
  • 英文版
    High Frequency System Clock Generator
    ICST [Integrate...
  • 英文版
    Rambus XDR Clock Generator
    ICST [Integrate...
  • 英文版
    Direct Rambus Clock Generator Lite
    ICS
  • 英文版
    Direct Rambus Clock Generator Lite
    ICST [Integrate...
  • 英文版
    133MHz Clock Generator and Integrated Buffer for PowerPC⑩
    ICS
  • 英文版
    133MHz Clock Generator and Integrated Buffer for PowerPC??
    ICST [Integrate...
  • 英文版
    133MHz Clock Generator and Integrated Buffer for PowerPC⑩
    ICS
  • 英文版
    133MHz Clock Generator and Integrated Buffer for PowerPC??
    ICST [Integrate...
  • 英文版
    Dual Voltage Video/Memory Clock Generator
    ICS
  • 英文版
    Dual Voltage Video/Memory Clock Generator
    ICST [Inte...
  • 英文版
    Analog IC
    ETC
  • 英文版
    Analog IC
    ETC
  • 英文版
    High Performance Communication Buffer
    ICS
  • 英文版
    High Performance Communication Buffer
    ICST [Inte...
  • 英文版
    High performance Communication Buffer
    ICS
  • 英文版
    High performance Communication Buffer
    ICST [Inte...
  • 英文版
    32 kHz Motherboard Frequency Generator
    ICS

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務：
賣家服務：
技術客服：

0571-85317607

網(wǎng)站技術支持

13606545031

客服在線時間周一至周五
9:00-17:30

關注官方微信號，
第一時間獲取資訊。

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務的動力！意見一經(jīng)采納，將有感恩紅包奉上哦！