VIA Pro266/PN266/CLE266/CM400 chipset for PIII/Tualatin/C3 鈥?/div>
Programmable output frequency.
Processor
鈥?/div>
Programmable output divider ratios.
鈥?/div>
Programmable output rise/fall time.
Output Features:
鈥?/div>
Programmable output skew.
鈥?/div>
1 - Pair of differential CPU clocks @ 3.3V (CK408)/
鈥?/div>
Programmable spread percentage for EMI control.
鈥?/div>
1 - Pair of differential open drain CPU clocks (K7)
鈥?/div>
Watchdog timer technology to reset system
鈥?/div>
2 - Push pull CPUT_CS clocks @ 2.5V
if system malfunctions.
鈥?/div>
3 - AGP @ 3.3V
鈥?/div>
Programmable watch dog safe frequency.
鈥?/div>
7 - PCI @ 3.3V
鈥?/div>
Support I
2
C Index read/write and block read/write
鈥?/div>
1 - 48MHz @ 3.3V fixed
operations.
鈥?/div>
1 - 24_48MHz @ 3.3V
鈥?/div>
Uses external 14.318MHz crystal.
鈥?/div>
2 - REF @ 3.3V, 14.318MHz
Key Specifications:
鈥?/div>
CPU_CS - CPUT/C: <鹵250ps
鈥?/div>
CPU_CS - AGP: <鹵250ps
鈥?/div>
CPU - DDR/SD: <鹵250ps
鈥?/div>
PCI - PCI: <500ps
Frequency Table
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPUCLK
MHz
160.00
164.00
166.60
170.00
175.00
180.00
185.00
190.00
66.80
100.90
133.60
200.40
66.60
100.00
200.00
133.30
AGP
MHz
80.00
82.00
66.60
68.00
70.00
72.00
74.00
76.00
66.80
67.27
66.80
66.80
66.60
66.60
66.60
66.60
PCICLK
MHz
40.00
41.00
33.30
34.00
35.00
36.00
37.00
38.00
33.40
33.63
33.40
33.40
32.30
33.30
33.30
33.30
Pin Configuration
*FS0/REF0 1
GND 2
X1 3
X2 4
VDDAGP 5
*MODE/AGPCLK0 6
*SEL_408/K7/AGPCLK1
7
*(PCI_STOP#)AGPCLK2
8
GNDAGP
9
**FS1/PCICLK_F
10
**SEL_SDR/DDR#/PCICLK1
11
GNDPCI
13
PCICLK3
14
PCICLK4
15
VDDPCI 16
PCICLK5 17
*(CLK_STOP#)/PCICLK6 18
GND48 19
*FS3/48MHz 20
*FS2/24_48MHz 21
AVDD48 22
VDD 23
*MULTSEL/PCICLK2
12
56 Vtt_PWRGD#**/REF1
55 VDDREF
54 GND
53 CPUCLKT/CPUCLKODT
52 CPUCLKC/CPUCLKODC
51 VDDCPU3.3
50 VDDCPU2.5
49 CPUT0_CS
48 CPUT1_CS
47 GND
46 FBOUT
45 BUF_IN
44 DDRT0/SDRAM0
43 DDRC0/SDRAM1
42 DDRT1/SDRAM2
41 DDRC1/SDRAM3
40 VDD3.3_2.5
39 GND
38 DDRT2/SDRAM4
37 DDRC2/SDRAM5
36 DDRT3/SDRAM6
35 DDRC3/SDRAM7
34 VDD3.3_2.5
33 GND
32 DDRT4/SDRAM8
31 DDRC4/SDRAM9
30 DDRT5/SDRAM10
29 DDRC5/SDRAM11
MULTISEL0
Board Target
Trace/Term Z
50 ohms
50 ohms
Reference R,
Iref =
V
DD
/(3*Rr)
Rr = 221 1%,
Iref = 5.00mA
Rr = 475 1%,
Iref = 2.32mA
Output
Current
Ioh = 4* I REF
Ioh = 6* I REF
Voh @ Z
GND 24
IREF 25
*(PD#)RESET# 26
SCLK 27
SDATA 28
0
1
1.0V @ 50
0.7V @ 50
* Internal 120K pull-up resistor to VDD.
** Internal 120K pull-down resistor to GND.
56-Pin 300-mil SSOP
0653A鈥?7/26/04
PRODUCT PREVIEW
documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to
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