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ICS950905 Datasheet

  • ICS950905

  • Programmable Timing Control Hub⑩ for P4⑩

  • 18頁(yè)

  • ICS

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Integrated
Circuit
Systems, Inc.
ICS950905
Advance Information
Programmable Timing Control Hub鈩?for P4鈩?/div>
Recommended Application:
VIA P4X266 chipset with PC133 or DDR memory.
Output Features:
鈥?/div>
2 - Pair of differential CPU clocks @ 3.3V
鈥?/div>
1 - Pair of differential push pull CPU_CS clocks @ 2.5V
鈥?/div>
3 - AGP @ 3.3V
鈥?/div>
9 - PCI @ 3.3V
鈥?/div>
1- IOAPIC @ 2.5V
鈥?/div>
1 - 48MHz @ 3.3V fixed
鈥?/div>
1 - 24_48MHz @ 3.3V
鈥?/div>
1 - REF @ 3.3V, 14.318MHz
Features/Benefits:
鈥?/div>
Programmable output frequency.
鈥?/div>
Programmable output divider ratios.
鈥?/div>
Programmable output rise/fall time.
鈥?/div>
Programmable output skew.
鈥?/div>
Programmable spread percentage for EMI control.
鈥?/div>
Watchdog timer technology to reset system
if system malfunctions.
鈥?/div>
Programmable watch dog safe frequency.
鈥?/div>
Support I
2
C Index read/write and block read/write
operations.
鈥?/div>
For DDR and or PC133 SDRAM system use ICS93718
as the memory buffer.
鈥?/div>
Uses external 14.318MHz crystal.
Key Specifications:
鈥?/div>
CPU_CS - CPU0: <鹵250ps
鈥?/div>
CPU_CS - AGP: <鹵250ps
鈥?/div>
PCI - PCI: <500ps
鈥?/div>
CPU - PCI: Min = 1.0ns, Typ = 2.0ns, Max = 4.0ns
Pin Configuration
**SEL24_48/REF0
VDDREF
GND
X1
X2
VDD48
*FS3/48MHz
*FS2/24_48MHz
GND
*FS0/PCICLK_F
**FS1/PCICLK0
*MULTI_SEL/PCICLK1
GND
*WDTB/PCICLK2
**WDEN/PCICLK3
VDDPCI
PCICLK4
PCICLK5
PCICLK6
GND
PCICLK7
*PD#
AGPCLK0
VDDAGP
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDLAPIC
GND
N/C
IOAPIC
GND
VDDCPU_PP (2.5V)
CPUCLK_PPT
CPUCLK_PPC
CPUCLKT_0
CPUCLKC_0
VDDCPU (3.3V)
I REF
GND
CPUCLKT_1
CPUCLKC_1
Vtt_PWRGD#
CPU_STOP#*
PCI_STOP#*
RESET#
SDATA
SCLK
AGPCLK2
AGPCLK1
GND
48-Pin 300-mil SSOP
1. These outputs have 2X drive strength.
* These inputs have a internal Pull-up resistor
of 120K to VDD
** These inputs have a internal pull-down to GND
Frequency Table
FS 3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FS 2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FS 1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Board Target
Trace/Term Z
50 ohms
50 ohms
ICS950905
FS 0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPUCLK
MHz
160.00
164.00
166.60
170.00
175.00
180.00
185.00
190.00
66.80
100.90
133.60
200.40
66.60
100.00
200.00
133.30
AGP
MHz
80.00
82.00
66.60
68.00
70.00
72.00
74.00
76.00
66.80
67.27
66.80
66.80
66.60
66.60
68.60
68.60
Output
Current
Ioh = 4* I REF
Ioh = 6* I REF
PCICLK
MHz
40.00
41.00
33.30
34.00
35.00
36.00
37.00
38.00
33.40
33.63
33.40
33.40
32.30
33.30
33.30
33.30
Block Diagram
PLL2
/2
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
48MHz
24_48MHz
REF0
CPU
DIVDER
Stop
CPUCLKT_(1:0)
CPUCLKC_(1:0)
CPUCLK_PPT
CPUCLK_PPC
IOAPIC
CPU
DIVDER
Stop
SEL24_48
SDATA
SCLK
FS (3:0)
PD#
PCI_STOP#
CPU_STOP#
MULTI_SEL
Vtt_PWRGD#
WDEN
WDTB
Control
Logic
IOAPIC
DIVDER
PCI
DIVDER
Stop
PCICLK (7:0)
PCICLK_F
Config.
Reg.
AGP
DIVDER
3
AGPCLK (2:0)
RESET#
I REF
MULTISEL0
Reference R,
Iref =
V
DD
/(3*Rr)
Rr = 221 1%,
Iref = 5.00mA
Rr = 475 1%,
Iref = 2.32mA
Voh @ Z
0
1
1.0V @ 50
0.7V @ 50
950905 Rev - 11/26/01
ADVANCE INFORMATION
documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.

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