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ICS950812YFLFT Datasheet

  • ICS950812YFLFT

  • Frequency Generator with 200MHz Differential CPU Clocks

  • 225.66KB

  • 29頁(yè)

  • ICS

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Integrated
Circuit
Systems, Inc.
ICS950812
Frequency Generator with 200MHz Differential CPU Clocks
Recommended Application:
Pin Configuration
CK-408 clock with Buffered/Unbuffered mode supporting
VDDREF 1
56 REF
Almador, Brookdale, ODEM, and Montara-G chipsets with
X1 2
55 FS1
PIII/P4 processor. Programmable for group to group skew.
X2 3
54 FS0
Output Features:
GND 4
53 CPU_STOP#*
PCICLK_F0 5
52 CPUCLKT0
鈥?/div>
3 Differential CPU Clock Pairs @ 3.3V
PCICLK_F1 6
51 CPUCLKC0
鈥?/div>
7 PCI (3.3V) @ 33.3MHz including 2 early PCI clocks
PCICLK_F2 7
50 VDDCPU
鈥?/div>
3 PCI_F (3.3V) @ 33.3MHz
VDDPCI 8
49 CPUCLKT1
GND 9
48 CPUCLKC1
鈥?/div>
1 USB (3.3V) @ 48MHz, 1 DOT (3.3V) @ 48MHz
PCICLK0 10
47 GND
鈥?/div>
1 REF (3.3V) @ 14.318MHz
**E_PCICLK1/PCICLK1 11
46 VDDCPU
鈥?/div>
5 3V66 (3.3V) @ 66.6MHz
PCICLK2 12
45 CPUCLKT2
**E_PCICLK3/PCICLK3 13
44 CPUCLKC2
鈥?/div>
1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz
VDDPCI 14
43 MULTSEL*
鈥?/div>
3 66MHz_OUT/3V66 (3.3V) @ 66.6MHz_IN or 66.6MHz
GND 15
42 IREF
PCICLK4 16
41 GND
Features:
PCICLK5 17
40 FS2
鈥?/div>
Provides standard frequencies and additional 5%
PCICLK6 18
39 48MHz_USB/FS3
**
and 10% over-clocked frequencies
VDD3V66 19
38 48MHz_DOT
鈥?/div>
Supports spread spectrum modulation:
GND 20
37 VDD48
No spread, Center Spread (鹵0.35%, 鹵0.5%,
66MHZ_OUT0/3V66_2 21
36 GND
or 鹵0.75%), or Down Spread (-0.5%, -1.0%, or -1.5%)
66MHZ_OUT1/3V66_3 22
35 3V66_1/VCH_CLK/FS4
**
66MHZ_OUT2/3V66_4 23
34 PCI_STOP#*
鈥?/div>
Offers adjustable PCI early clock via latch inputs
66MHZ_IN/3V66_5 24
33 3V66_0/FS5
**
鈥?/div>
Selectable 1X or 2X strength for REF via I
2
C interface
*PD# 25
32 VDD3V66
VDDA 26
31 GND
鈥?/div>
Efficient power management scheme through PD#,
GND 27
30 SCLK
CPU_STOP# and PCI_STOP#.
Vtt_PWRGD# 28
29 SDATA
鈥?/div>
Uses external 14.318MHz crystal
鈥?/div>
Stop clocks and functional control available through
56-Pin 300mil SSOP
I
2
C interface.
6.10 mm. Body, 0.50 mm. pitch TSSOP
Key Specifications:
*
These inputs have 120K internal pull-up resistors to VDD.
鈥?/div>
CPU Output Jitter <150ps
**
Internal pull-down resistors to ground.
鈥?/div>
3V66 Output Jitter <250ps
Note:
鈥?/div>
66MHz Output Jitter (Additive) (Buffered Mode) <100ps
Almador board level designs MUST use pin 22,
鈥?/div>
CPU Output Skew <100ps
66MHZ_OUT1, as the feedback connection from the
clock buffer path to the Almador (GMCH) chipset.
PLL2
48MHz_USB
48MHz_DOT
X1
X2
XTAL
OSC
Block Diagram
Frequency Select
Bit
FS2 FS1 FS0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
CPUCLK
MHz
66.66
100.00
200.00
133.33
66.66
100.00
200.00
133.33
3V66
MHz
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66MHz_OU
T (2:0)
3V66 (4:2)
MHz
66.66
66.66
66.66
66.66
66MHz_IN
66MHz_IN
66MHz_IN
66MHz_IN
66MHz_IN
3V66_5
MHz
66.66
66.66
66.66
66.66
Input
Input
Input
Input
PCICLK_F
PCICLK
MHz
33.33
33.33
33.33
33.33
66MHz_IN/2
66MHz_IN/2
66MHz_IN/2
66MHz_IN/2
3V66_5/66MHz_IN
3V66_3/66MHz_OUT1
3V66_(4,2)/66MHz_OUT(2,0)
PLL1
Spread
Spectrum
PD#
CPU_STOP#
PCI_STOP#
MULTSEL
FS (5:0)
SDATA
SCLK
V
TT
_PWRGD#
REF
CPU
DIVDER
Stop
3
3
CPUCLKT (2:0)
CPUCLKC (2:0)
PCICLK (6:4, 2, 0)
PCI
DIVDER
Stop
7
Control
Logic
3V66
DIVDER
2
E_PCICLK(1,3)/PCICLK(1,3)
(2:0)
3
PCICLK_F
3V66_0
Config.
Reg.
3V66_1/VCH_CLK
I REF
0542G鈥?8/21/03
ICS950812

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