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ICS950208 Datasheet

  • ICS950208

  • Programmable Timing Control Hub for P4

  • 19頁

  • ICS

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Integrated
Circuit
Systems, Inc.
ICS950208
Programmable Timing Control Hub鈩?for P4鈩?/div>
Recommended Application:
CK-408 clock with driven mode only for Brookdale chipset with
P4 processor.
Output Features:
鈥?/div>
3 - Pairs of differential CPU clocks @ 3.3V
鈥?/div>
4 - 3V66 @ 3.3V
鈥?/div>
10 - PCI @ 3.3V
鈥?/div>
1 - 48MHz @ 3.3V fixed
鈥?/div>
1 - 24_48MHz selectable output @ 3.3V
鈥?/div>
2 - REF @ 3.3V, 14.318MHz
Features/Benefits:
鈥?/div>
Programmable output frequency.
鈥?/div>
Programmable output divider ratios.
鈥?/div>
Programmable output rise/fall time.
鈥?/div>
Programmable output skew.
鈥?/div>
Programmable spread percentage for EMI control.
鈥?/div>
Watchdog timer technology to reset system
if system malfunctions.
鈥?/div>
Programmable watch dog safe frequency.
鈥?/div>
Supports I
2
C Index read/write and block read/write
operations.
鈥?/div>
Uses external 14.318MHz crystal.
Key Specifications:
鈥?/div>
CPU Output Jitter <150ps
鈥?/div>
3V66 Output Jitter <250ps
鈥?/div>
CPU Output Skew <100ps
Pin Configuration
*MULTSEL1/REF1 1
VDDREF 2
X1 3
X2 4
GND 5
*FS2/PCICLK_F0 6
*FS3/PCICLK_F1 7
PCICLK_F2 8
VDDPCI 9
PCICLK1 11
PCICLK2 12
GND 13
PCICLK3 14
PCICLK4 15
PCICLK5 16
PCICLK6 17
VDDPCI 18
Vttpwr_GD# 19
RESET# 20
GND 21
*FS0/48MHz 22
*FS1/24_48MHz 23
AVDD48 24
*FS4/PCICLK0 10
48 REF0/MULTSEL0*
47 GNDREF
46 VDDCPU
45 CPUCLKT2
44 CPUCLKC2
43 GNDCPU
42 PD#
41 CPUCLKT0
40 CPUCLKC0
39 VDDCPU
38 CPUCLKT1
37 CPUCLKC1
36 GNDCPU
35 IREF
34 AVDD
33 GND
32 VDD3V66
31 3V66_0
30 3V66_1
29 GND
28 3V66_2
27 3V66_3
26 SCLK
25 SDATA
48-SSOP
* Internal Pull-Up Resistor of 120K to VDD
Frequency Table
Bit2
FS4
0
0
0
0
0
0
0
0
0
Bit7
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Bit6
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Bit5
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Bit4
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPU
MHz
102.00
105.00
108.00
111.00
114.00
117.00
120.00
123.00
126.00
130.00
136.00
140.00
144.00
148.00
152.00
156.00
160.00
164.00
166.60
170.00
175.00
180.00
185.00
190.00
66.80
100.20
133.60
200.40
66.60
100.00
200.00
133.33
3V66
MHz
68.00
70.00
72.00
74.00
76.00
78.00
80.00
82.00
72.00
74.30
68.00
70.00
72.00
74.00
76.00
78.00
80.00
82.00
66.60
68.00
70.00
72.00
74.00
76.00
66.80
66.80
66.80
66.80
66.60
66.60
66.60
66.60
PCI
MHz
34.00
35.00
36.00
37.00
38.00
39.00
40.00
41.00
36.00
37.10
34.00
35.00
36.00
37.00
38.00
39.00
40.00
41.00
33.30
34.00
35.00
36.00
37.00
38.00
33.40
33.40
33.40
33.40
33.30
33.30
33.30
33.30
Block Diagram
PLL2
/2
48MHz
24_48MHz
REF (1:0)
0
0
0
0
0
0
0
1
1
1
X1
X2
XTAL
XTAL
OSC
PLL1
Spread
Spectrum
Spectrum
Control
Logic
CPU
DIVDER
3
3
CPUCLKT (2:0)
CPUCLKC (2:0)
PCI
PCICLK (6:0), PCICLK_F (1:0)
3V66 (3:0)
RESET#
I REF
1
1
1
PCI
DIVDER
10
1
1
PD#
MULTSEL(1:0)
MULTSEL(1:0)
FS (4:0)
SDATA
SD
SCLK
Vtt_PWRGD#
3V66
DIVDER
1
1
1
1
1
1
1
1
4
Config.
Reg.
0464B鈥?8/04/03
ICS950208

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