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ICS950202 Datasheet

  • ICS950202

  • Programmable Timing Control HubTM for P4TM

  • 19頁(yè)

  • ICS

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Integrated
Circuit
Systems, Inc.
ICS950202
Programmable Timing Control Hub
TM
for P4
TM
Recommended Application:
CK-408 clock for Intel廬 845 chipset.
Output Features:
鈥?/div>
3 - Pairs of differential CPU clocks @ 3.3V
鈥?/div>
3 - 3V66 @ 3.3V
鈥?/div>
9 - PCI @ 3.3V
鈥?/div>
2 - 48MHz @ 3.3V fixed
鈥?/div>
1 - VCH/3V66 @ 3.3V, 48MHz or 66MHz
鈥?/div>
1 - REF @ 3.3V, 14.318MHz
Features/Benefits:
鈥?/div>
Programmable output frequency.
鈥?/div>
Programmable output divider ratios.
鈥?/div>
Programmable output rise/fall time.
鈥?/div>
Programmable output skew.
鈥?/div>
Programmable spread percentage for EMI control.
鈥?/div>
Watchdog timer technology to reset system
if system malfunctions.
鈥?/div>
Programmable watch dog safe frequency.
鈥?/div>
Support I
2
C Index read/write and block read/write
operations.
鈥?/div>
Uses external 14.318MHz crystal.
Key Specifications:
鈥?/div>
CPU Output Jitter <150ps
鈥?/div>
3V66 Output Jitter <250ps
鈥?/div>
CPU Output Skew <100ps
VDDREF
X1
X2
GND
1
**FS0/PCICLK7
1
**FS1/PCICLK8
VDDPCI
GND
1
*WDEN/PCICLK0
PCICLK1
PCICLK2
PCICLK3
VDDPCI
GND
PCICLK4
PCICLK5
PCICLK6
VDD3V66
GND
3V66_1
3V66_2
3V66_3
#RESET
VDDA
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
REF/FS2**
CPUCLKT0
CPUCLKC0
VDDCPU
CPUCLKT1
CPUCLKC1
GND
VDDCPU
CPUCLKT2
CPUCLKC2
MULTISEL0*
I REF
GND
48MHz_USB/FS3**
48MHz_DOT
AVDD48
GND
3V66_0/VCH_CLK/FS4**
VDD3V66
GND
SCLK
SDATA
Vtt_PWRGD/PD#
GND
1
48-Pin 300-mil SSOP
1. These outputs have 2X drive strength.
* Internal Pull-up resistor of 120K to VDD
** these inputs have 120K internal pull-down
to GND
Block Diagram
Frequency Table
FS4 FS3 FS2 FS1 FS0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
0
1
CPUCLK
MHz
100.00
133.33
66.67
200.00
3V66
MHz
66.67
66.67
66.67
66.67
PCICLK
MHz
33.33
33.33
33.34
33.33
For additional frequency selections please refer to Byte 0.
Power Groups
VDDA = Analog Core PLL
VDDREF = REF, Xtal
AVDD48 = 48MHz
0461L鈥?5/28/03
ICS950202

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