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Integrated

Circuit

Systems, Inc.

ICS93V855

DDR Phase Lock Loop Clock Driver

Recommended Application:

DDR Clock Driver

Product Description/Features:

鈥?Low skew, low jitter PLL clock driver

鈥?External feedback pins for input to output

synchronization

鈥?Spread Spectrum tolerant inputs

鈥?With bypass mode mux

鈥?Operating frequency 60 to 170 MHz

Switching Characteristics:

鈥?CYCLE - CYCLE jitter:<75ps

鈥?OUTPUT - OUTPUT skew: <60ps

鈥?Output Rise and Fall Time: 650ps - 950ps

Pin Configuration

GND

DDRC0

DDRT0

VDD2.5

CLK_INT

CLK_INC

AVDD2.5

AGND

GND

DDRC1

DDRT1

VDD2.5

DDRT2

DDRC2

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

DDRC4

DDRT4

VDD2.5

GND

FB_OUTC

FB_OUTT

VDD2.5

FB_INT

FB_INC

GND

VDD2.5

DDRT3

DDRC3

GND

28-Pin 4.4mm TSSOP

Block Diagram

FB_OUTT

FB_OUTC

DDRT0

DDRC0

DDRT1

DDRC1

Functionality

INPUTS

GND

GND

2.5V

(nom)

2.5V

(nom)

L

H

L

H

H

L

H

L

L

H

L

H

Hi-Z

H

L

H

L

Hi-Z

OUTPUTS

L

H

L

H

Hi-Z

H

L

H

L

Hi-Z

AVDD CLK_INT CLK_INC DDRT DDRC FB_OUTT FB_OUTC

PLL State

Bypassed/Off

Bypassed/Off

On

On

Off

Control

Logic

DDRT2

DDRC2

DDRT3

DDRC3

DDRT4

DDRC4

2.5V

<20 MHz <20 MHz

(nom)

FB_INT

FB_INC

CLK_INC

CLK_INT

PLL

AVDD2.5

0497B鈥?6/01/04

ICS93V855

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