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Integrated

Circuit

Systems, Inc.

ICS93776

Low Cost DDR Phase Lock Loop Zero Delay Buffer

Recommended Application:

DDR Zero Delay Clock Buffer

Product Description/Features:

鈥?Low skew, low jitter PLL clock driver

鈥?Max frequency supported = 266MHz (DDR 533)

鈥?I

2

C for functional and output control

鈥?Feedback pins for input to output synchronization

鈥?Spread Spectrum tolerant inputs

鈥?3.3V tolerant CLK_INT/C input

Switching Characteristics:

鈥?CYCLE - CYCLE jitter: <100ps

鈥?OUTPUT - OUTPUT skew: <100ps

鈥?DUTY CYCLE: 48% - 52%

Pin Configuration

DDRC0

DDRT0

VDD

DDRT1

DDRC1

GND

SCLK

CLK_INT

CLK_INC

VDDA

GND

VDD

DDRT2

DDRC2

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

GND

DDRC5

DDRT5

DDRC4

DDRT4

VDD

SDATA

FB_INC

FB_INT

FB_OUTT

FB_OUTC

DDRT3

DDRC3

GND

28-Pin 209mil SSOP

Block Diagram

FB_OUTT

FB_OUTC

Functionality

INPUTS

2.5V

(nom)

2.5V

(nom)

OUTPUTS

AVDD CLK_INT CLKT CLKC FB_OUTT

L

H

L

H

H

L

L

H

PLL State

on

on

SCLK

SDA

SDATA

Control

Logic

DDRT0

DDRC0

DDRT1

DDRC1

DDRT2

DDRC2

FB_INC

FB_INT

PLL

CLK_INT

CLK_INC

DDRT3

DDRC3

DDRT4

DDRC4

DDRT5

DDRC5

0793A鈥?3/08/05

ADVANCE INFORMATION

documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.

ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.

ICS93776

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