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Integrated

Circuit

Systems, Inc.

ICS93722

Low Cost DDR Phase Lock Loop Zero Delay Buffer

Recommended Application:

DDR Zero Delay Clock Buffer

Product Description/Features:

鈥?Low skew, low jitter PLL clock driver

鈥?I

2

C for functional and output control

鈥?Feedback pins for input to output synchronization

鈥?Spread Spectrum tolerant inputs

鈥?3.3V tolerant CLK_INT input

Switching Characteristics:

鈥?PEAK - PEAK jitter (66MHz): <120ps

鈥?PEAK - PEAK jitter (>100MHz): <75ps

鈥?CYCLE - CYCLE jitter (66MHz):<110ps

鈥?CYCLE - CYCLE jitter (>100MHz):<65ps

鈥?OUTPUT - OUTPUT skew: <100ps

鈥?Output Rise and Fall Time: 650ps - 950ps

鈥?DUTY CYCLE: 49.5% - 50.5%

Pin Configuration

CLKC0

CLKT0

VDD

CLKT1

CLKC1

GND

SCLK

CLK_INT

N/C

VDDA

GND

VDD

CLKT2

CLKC2

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

GND

CLKC5

CLKT5

CLKC4

CLKT4

VDD

SDATA

N/C

FB_INT

FB_OUTT

N/C

CLKT3

CLKC3

GND

28-Pin SSOP

Block Diagram

Functionality

INPUTS

AVDD

FB_OUTT

OUTPUTS

CLKT CLKC FB_OUTT

L

H

Z

H

L

Z

L

H

Z

ICS93722

CLK_INT

L

H

<20MHz

PLL State

on

on

off

2.5V

(nom)

2.5V

(nom)

2.5V

(nom)

SCLK

SDATA

Control

Logic

CLKT0

CLKC0

CLKT1

CLKC1

CLKT2

CLKC2

FB_INT

PLL

CLK_INT

CLKT3

CLKC3

CLKT4

CLKC4

CLKT5

CLKC5

0539E鈥?7/18/03

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