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ICS93718YFT Datasheet

  • ICS93718YFT

  • DDR and SDRAM Buffer

  • 8頁

  • ICS

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Integrated
Circuit
Systems, Inc.
ICS93718
DDR and SDRAM Buffer
Recommended Application:
DDR & SDRAM fanout buffer, for VIA Pro 266, KT266 and
P4X266 DDR chipsets
Product Description/Features:
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Low skew, fanout buffer
1 to 12 differential clock distribution
I
2
C for functional and output control
Feedback pin for input to output synchronization
Supports up to 4 DDR DIMMs or 3 SDRAM DIMMs +
2 DDR DIMMs
Frequency supports up to 200MHz (DDR400)
Supports Power Down Mode for power
mananagement
CMOS level control signal input
Pin Configuration
FB_OUT
VDD3.3_2.5
GND
DDRT0_SDRAM0
DDRC0_SDRAM1
DDRT1_SDRAM2
DDRC1_SDRAM3
VDD3.3_2.5
GND
DDRT2_SDRAM4
DDRC2_SDRAM5
VDD3.3_2.5
BUF_IN
GND
DDRT3_SDRAM6
DDRC3_SDRAM7
VDD3.3_2.5
GND
DDRT4_SDRAM8
DDRC4_SDRAM9
DDRT5_SDRAM10
DDRC5_SDRAM11
VDD3.3_2.5
SDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SEL_DDR*
VDD2.5
GND
DDRT11
DDRC11
DDRT10
DDRC10
VDD2.5
GND
DDRT9
DDRC9
VDD2.5
PD#*
GND
DDRT8
DDRC8
VDD2.5
GND
DDRT7
DDRC7
DDRT6
DDRC6
GND
SCLK
Switching Characteristics:
鈥?OUTPUT - OUTPUT skew: <100ps
鈥?Output Rise and Fall Time for DDR outputs: 500ps -
700ps
鈥?DUTY CYCLE: 47% - 53%
48-Pin SSOP
*Internal Pull-up Resistor of 120K to VDD
Block Diagram
FB_OUT
DDRT0_SDRAM0
DDRC0_SDRAM1
DDRT1_SDRAM2
DDRC1_SDRAM3
Functionality
MODE
DDR
Mode
DDR/SD
Mode
PIN 48
VDD
3.3_2.5
2.5V
PIN
4, 5, 6, 7, 10, 11, 15,
16, 19, 20, 21, 22
These outputs will be
DDR outputs
These outputs will be
standard SDRAM
outputs
BUF_IN
SEL_DDR=1
SCLK
SDATA
SEL_DDR*
PD#
Control
Logic
DDRT2_SDRAM4
DDRC2_SDRAM5
DDRT3_SDRAM6
DDRC3_SDRAM7
DDRT4_SDRAM8
DDRC4_SDRAM9
DDRT5_SDRAM10
DDRC5_SDRAM11
DDRT(11:6)
DDRC (11:6)
SEL_DDR=0
3.3V
0434D鈥?0/10/03
ICS93718

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