鈥?/div>
PCI Output Jitter: <500ps
Pin Configuration
VDDREF
REF1
REF0
GNDREF
X1
X2
*PD#
*CPU-STOP#
VDD
GND
*PCI_STOP#
*SS_EN#
VDDPCI
PCIREF
GNDPCI
*FS0
*FS1
*FS2
VDDFP
GNDFP
*TEST#/OUT
*BOOST#/OUT_DIV2
*PDFP#
VDDA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
OUTSEL1*
VDDCPU
GNDCPU
CPU0
CPU1
CPU2
VDDCPU
GNDCPU
CPU3
CPU4
CPU5
VDDCPU
GNDCPU
CPU6
CPU7
CPU8
VDDCPU
GNDCPU
CPU9
CPU10
CPU11
VDDCPU
GNDCPU
OUTSEL0*
48-Pin 300mil SSOP
* Internal pull-up resistor of 120K to VDD
on indicated inputs.
Block Diagram
PLL2
/2
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
OUT
OUT/DIV2
Functionality
TEST
1
2
ICS9342
CPU
MHz
133.33
100.00
83.33
66.66
133.33
100.00
83.33
66.66
FS2
1
1
1
1
0
0
0
0
FS1
1
1
0
0
1
1
0
0
FS0
1
0
1
0
1
0
1
0
PCI
MHz
33.33
33.33
33.33
33.33
66.66
66.66
66.66
66.66
REF
MHz
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
REF (1:0)
1
1
1
1
1
CPU
DIVDER
Stop
12
CPUCLK (11:0)
OUTSEL (1:0)
SS_EN#
Control
Logic
FS (2:0)
PD#
PDFP#
TEST#
BOOST#
PCI
DIVDER
Stop
PCIREF
1
1
Config.
Reg.
9342 Rev E 9/06/00
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ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.