鈥?/div>
IOAPIC Output Jitter: <500ps
48MHz, 3V66, PCI Output Jitter: <500ps
Ref Output Jitter. <1000ps
CPU Output Skew: <175ps
IOAPIC Output Skew <250ps
PCI Output Skew: <500ps
3V66 Output Skew <250ps
CPU to 3V66 Output Offset: 0.8 - 1.8ns (typ =
1.3ns)
CPU to PCI Output Offset: 0.0 - 1.5ns (typ =
0.9ns)
CPU to IOAPIC Output Offset: 1.5 - 4.0ns (typ =
2.0ns)
Block Diagram
PLL2
/2
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
48MHz
24_48MHz
Pin Configuration
GNDREF
REF0
*SEL24_48#/REF1
VDDREF
X1
X2
GNDPCI
*FS0/PCICLK0
*FS1/PCICLK1
VDDPCI
*FS2/PCICLK2
*FS3/PCICLK3
GNDPCI
PCICLK4
PCICLK5
VDDPCI
PCICLK6
PCICLK7
GNDPCI
PCICLK8
PCICLK9
PCICLK10
VDDPCI
PD#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDLAPIC
IOAPIC0
IOAPIC1
GNDLAPIC
IOAPIC2
VDDLCPU
CPUCLK0
GNDLCPU
CPUCLK1
VDDLCPU
CPU_CSCLK0
CPU_CSCLK1
GNDLCPU
VDD66
3V66_0
3V66_1
3V66_2
GND66
SDATA
SCLK
VDD48
48MHz/FS4*
24_48MHz
GND48
REF (1:0)
CPU
DIVDER
CPUCLK (1:0)
CPU_CSCLK (1:0)
IOAPIC
DIVDER
IOAPIC (2:0)
SEL24_48#
SDATA
SCLK
FS (4:0)
PD#
Control
Logic
Config.
Reg.
PCI
DIVDER
PCICLK (10:0)
3V66
DIVDER
3V66 (2:0)
48-pin SSOP
*120K ohm pull-up to VDD on indicated inputs.
0600A鈥?8/04/03
ICS932S202