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ICS9250YF-30-T Datasheet

  • ICS9250YF-30-T

  • Frequency Generator & Integrated Buffers for Celeron & PII/I...

  • 13頁

  • ICS

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Integrated
Circuit
Systems, Inc.
ICS9250-30
Preliminary Product Preview
Frequency Generator & Integrated Buffers for Celeron & PII/III鈩?/div>
Recommended Application:
810/810E and Solano type chipset
Output Features:
鈥?/div>
2 - CPUs @ 2.5V, up to 200MHz.
鈥?/div>
13 - SDRAM @ 3.3V, up to 200MHz.
鈥?/div>
3 - 3V66 @ 3.3V, 2x PCI MHz.
鈥?/div>
8 - PCI @3.3V.
鈥?/div>
1 - 48MHz, @3.3V fixed.
鈥?/div>
1 - 24/48MHz @ 3.3V
鈥?/div>
1 - REF @3.3V, 14.318MHz.
Features:
鈥?/div>
Support PC133 SDRAM.
鈥?/div>
Up to 200MHz frequency support
鈥?/div>
Support power management through PD#.
鈥?/div>
Spread spectrum for EMI control
(鹵 0.25% Center Spread or 0 to -0.5% down spread)
鈥?/div>
Uses external 14.318MHz crystal
鈥?/div>
FS pins for frequency select
Key Specifications:
鈥?/div>
CPU Output Jitter: <250ps
鈥?/div>
CPU Output Skew: <175ps
鈥?/div>
PCI Output Skew: <500ps
鈥?/div>
3V66 Output Skew <175ps
鈥?/div>
For group skew timing, please refer to the
Group Timing Relationship Table.
Pin Configuration
VDDREF
X1
X2
GNDREF
GND3V66
3V66-0
3V66-1
3V66-2
VDD3V66
VDDPCI
1
*FS0/PCICLK0
1
*FS1/PCICLK1
1
*SEL24_48#/PCICLK2
GNDPCI
PCICLK3
PCICLK4
PCICLK5
VDDPCI
PCICLK6
PCICLK7
GNDPCI
PD#
SCLK
SDATA
VDDSDR
SDRAM11
SDRAM10
GNDSDR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
REF0/FS4*
VDDLAPIC
IOAPIC
VDDLCPU
CPUCLK0
CPUCLK1
GNDLCPU
GNDSDR
SDRAM0
SDRAM1
SDRAM2
VDDSDR
SDRAM3
SDRAM4
SDRAM5
GNDSDR
SDRAM6
SDRAM7
SDRAM_F
VDDSDR
GND48
1
24_48MHz/FS2 *
1
48MHz/FS3*
VDD48
VDDSDR
SDRAM8
SDRAM9
GNDSDR
1
56-Pin 300 mil SSOP
1. These pins will have 1.5 to 2X drive strength.
* 120K ohm pull-up to VDD on indicated inputs.
Block Diagram
PLL2
/2
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
Functionality
48MHz
24_48MHz
REF0
CPU
DIVDER
2
CPUCLK [1:0]
SDRAM
DIVDER
12
SDRAM [11:0]
SDRAM_F
FS[4:0]
PD#
SEL24_48#
SDATA
SCLK
Control
Logic
Config.
Reg.
IOAPIC
DIVDER
IOAPIC
PCI
DIVDER
8
PCICLK [7:0]
FS4 FS3 FS2 FS1 FS0 CPU SDRAM
0
0
0
0
0
66.67
100.00
0
0
0
1
1
68.33
102.50
0
0
1
1
0
80.00
120.00
0
0
1
1
1
83.00
124.50
0
1
0
0
0 100.00 100.00
0
1
0
1
1 103.00 103.00
0
1
1
1
0 115.00 115.00
0
1
1
1
1 200.00 200.00
1
0
0
0
0 133.33 133.33
1
0
0
0
1 166.67 166.67
1
0
0
1
1 137.00 137.00
1
0
1
1
1 160.00 160.00
1
1
0
0
0 133.33 100.00
1
1
0
0
1 166.67 125.00
1
1
0
1
1 137.00 102.75
1
1
1
1
1 160.00 120.00
ICS9250-30
3V66
66.67
68.33
80.00
83.00
66.67
68.67
76.67
66.67
66.67
83.34
68.50
80.00
66.67
83.34
68.50
80.00
PCI
33.33
34.17
40.00
41.50
33.33
34.33
38.33
33.33
33.33
41.67
34.25
40.00
33.33
41.67
34.25
40.00
3V66
DIVDER
3
3V66 [2:0]
For other hardware/I
2
C selectable frequencies please refer to
Byte 0 frequency select register.
9250-30 Rev A 10/03/00
Third party brands and names are the property of their respective owners.
PRODUCT PREVIEW documents contain information on new products
in the sampling or preproduction phase of development. Characteristic
data and other specifications are subject to change without notice.

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